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1 december 9, 2005 idt82v2051e ? 2005 integrated device technology, inc. dsc-6528/2 idt and the idt logo are trademarks of integrated device technology, inc. single channel e1 short haul line in terface unit description the idt82v2051e is a single channel e1 line interface unit. the idt82v2051e performs clock/data recovery, ami/hdb3 line decoding and detects and reports the los conditions . an integrated adaptive equalizer is available to increase the rece ive sensitivity and enable programming of los levels. in transmit path, there is an ami/hdb3 encoder and waveform shaper. there is one jitter attenuator, wh ich can be placed in either the receive path or the transmit path. the jitter attenuator can also be disabled. the idt82v2051e supports both single rail and dual rail system inter- faces. to facilitate the network maintenance, a prbs generation/detection circuit is integrated in the chip, and different types of loopbacks can be set according to the applications. two diffe rent kinds of line terminating imped- ance, 75 ? and 120 ? are selectable. the chip also provides driver short- circuit protection and internal protec tion diode. the chip can be controlled by either software or hardware. the idt82v2051e can be used in lan, wan, routers, wireless base stations, iads, imas, imaps, gatewa ys, frame relay access devices, csu/dsu equipment, etc. features ? single channel e1 short haul line interfaces ? supports hps (hitless protection switching) for 1+1 protection without external relays ? single 3.3 v power supply with 5 v tolerance on digital interfaces ? meets or exceeds specifications in - ansi t1.102 - itu i.431, g.703, g.736, g.775 and g.823 - etsi 300-166, 300-233 and tbr12/13 ? software programmable or hardware selectable on: - wave-shaping templates - line terminating impedance (75 ?/ 120 ?) - adjustment of arbitrary pulse shape - ja (jitter attenuator) position (receive path or transmit path) - single rail/dual rail system interfaces - hdb3/ami line encoding/decoding - active edge of transmit clock (tclk) and receive clock (rclk) - active level of transmit data (tdata) and receive data (rdata) - receiver or transmitter power down - high impedance setti ng for line drivers - prbs (pseudo random bit sequence) generation and detection with 2 15 -1 prbs polynomials - 16-bit bpv (bipolar pulse violation) /excess zero/prbs error counter - analog loopback, digital loopback, remote loopback ? short circuit protection and internal protection diode for line drivers ? ais (alarm indicati on signal) detection ? supports serial control interface, motorola and intel multiplexed interfaces and hardware control mode ? pin compatibe to 82v2081 t1/e1/j1 long haul/short haul liu and 82v2041e t1/e1/j1 short haul liu ? package: available in 44-pin tqfp packages green package options available
idt82v2051e single channel e1 short haul line interface unit functional block diagram 2 december 9, 2005 functional block diagram figure-1 block diagram los rclk rd/rdp cv/rdn rtip rring tclk td/tdp tdn ttip tring jitter attenuator prbs generator taos prbs detector data and clock recovery data slicer adaptive equalizer los/ais detector hdb3/ami decoder digital loopback remote loopback jitter attenuator hdb3/ami decoder waveform shaper line driver analog loopback receiver internal termination transmitter internal termination clock generator register files software control interface pin control mode[1:0] term rxtxm[1:0] puls patt[1:0] ja[1:0] mont lp[1:0] thz rclke rpd rst vddio vddd vdda vddt mclk int cs sdo / ack / rdy sclk/ale/as rd / ds / sclke sdi/ wr /r/ w ad[7:0]
table of contents 3 december 9, 2005 1 idt82v2051e pin configurations ........ ................ ................ ............... .............. .............. ............ 8 2 pin description ............. ................. ................ ................ ................. ................ ............... .............. 9 3 functional description ............... ................. ................ .............. .............. .............. ............. ....... 15 3.1 control mode selection ............ ................. ................ .............. .............. .............. ............. 1 5 3.2 transmit path ............. ................. ................ ................ ................. ................ ............... ..... 15 3.2.1 transmit path system interfac e.................. ................. ................ ................. .......... 15 3.2.2 encoder................. ................ ................. ................ ................. ................ ............... 15 3.2.3 pulse shaper .............. ................ ................ ................. ................ ................. .......... 15 3.2.3.1 preset pulse templates .... ................ ................. .............. .............. ......... 15 3.2.3.2 user-programmable arbitrary waveform .. ............. .............. ............ ....... 16 3.2.4 transmit path line interface.. .............. .............. ............... .............. .............. .......... 17 3.2.5 transmit path power down ...... ................ ................ ................. ................ ............. 17 3.3 receive path .............. ................. ................ ................ ................. ................ ............... ..... 18 3.3.1 receive internal termination . .............. .............. ............... .............. .............. .......... 18 3.3.2 line monitor ............. ................. ................ ................ ................. ................ ............. 19 3.3.3 adaptive equalizer ...... ................ ................ ................. ................ ................. .......... 20 3.3.4 receive sensitivity............... ................ .............. ............... .............. .............. .......... 20 3.3.5 data slicer ............. ................ ................. ................ ................. ................ ............... 2 0 3.3.6 cdr (clock & data recovery)... ............... ................ ................. ................ ............. 20 3.3.7 decoder ................. ................ ................. ................ ................. ................ ............... 2 0 3.3.8 receive path system interfac e................. ................ ................. ................ ............. 21 3.3.9 receive path power down ....... ................ ................ ................. ................ ............. 21 3.4 jitter attenuator ........ ................ ................. ................ ................. ................ ................ ...... 21 3.4.1 jitter attenuation func tion descripton ............... ............... .............. .............. .......... 21 3.4.2 jitter attenuator performance ... ................ ................ ................. ................ ............. 22 3.5 los and ais detection ..... ................ ................. ................ ................. ................ ............... 22 3.5.1 los detection...... ................ ................ .............. ............... .............. .............. .......... 22 3.5.2 ais detection ........... ................. ................ ................ ................. ................ ............. 23 3.6 transmit and detect internal patt erns ........... .............. ............... .............. .............. .......... 24 3.6.1 transmit all ones ....... ................ ................ ................. ................ ................. .......... 24 3.6.2 transmit all zeros................ ................ .............. ............... .............. .............. .......... 24 3.6.3 prbs generation and detection............ .............. .............. .............. .............. ........ 24 3.7 loopback ............. ................. ................ .............. .............. .............. .............. ............. ....... 24 3.7.1 analog loopback ............ ................. ................ ................. .............. .............. .......... 24 3.7.2 digital loopback ........... ................ ................. ................ ................. .............. .......... 24 3.7.3 remote loopback........... ................. ................ ................. .............. .............. .......... 24 3.8 error detection/counting and insertion ......... .............. ............... .............. .............. .......... 27 table of contents
idt82v2051e single channel e1 short haul line interface unit table of contents 4 december 9, 2005 3.8.1 definition of line codi ng error ............... .............. .............. .............. .............. ........ 27 3.8.2 error detection and counting ... ................ ................ ................. ................ ............. 27 3.8.3 bipolar violation a nd prbs error insertion ..... ................. .............. .............. .......... 28 3.9 line driver failure monito ring ............... ................ ................. ................ ................. .......... 28 3.10 mclk and tclk ........... ................ ................ ................. ................ ................. ................ .29 3.10.1 master clock (mclk).... ................ ................. ................ ................. .............. .......... 29 3.10.2 transmit clock (tclk) .......... .............. .............. ............... .............. .............. .......... 29 3.11 microcontroller interfaces ....... ................ ................. .............. .............. .............. .............. .30 3.11.1 parallel microcontroller interf ace ................ ................. ................ ................. .......... 30 3.11.2 serial microcontroller interfac e ................. ................ ................. ................ ............. 30 3.12 interrupt handling ....... ................. ................ ................ ................. ................ ............... ..... 30 3.13 5v tolerant i/o pins ............. ................ ................ .............. ............... .............. .............. ... 31 3.14 reset operation .......... ................. ................ ................ ................. ................ ............... ..... 31 3.15 power supply ....... ................. ................ .............. .............. .............. .............. .............. ...... 31 4 programming information ....... ................ ................. ................ ................. ................ ............. .. 32 4.1 register list and map ..... ................ ................. ................ ................. ................ ............... 32 4.2 reserved registers ....... ................ ................ ................. ................ ................. ................ .32 4.3 register description ...... ................ ................ ................. ................ ................. ............... .. 33 4.3.1 control registers ........ ................ ................ ................. ................ ................. .......... 33 4.3.2 transmit path control registers............. .............. .............. .............. .............. ........ 35 4.3.3 receive path control registers........... .............. ............... .............. .............. .......... 37 4.3.4 network diagnostics co ntrol registers ........... ................. .............. .............. .......... 39 4.3.5 interrupt control registers..... .............. .............. ............... .............. .............. .......... 41 4.3.6 line status registers........... ................ .............. ............... .............. .............. .......... 43 4.3.7 interrupt status regi sters .................. ................ ............... .............. .............. .......... 45 4.3.8 counter registers ....... ................ ................ ................. ................ ................. .......... 46 5 hardware control pin summary ......... ................ ................ ............... .............. .............. .......... 47 6 test specifications .......... ................ ................ ................. ................ ................. .............. .......... 49 7 microcontroller interface timing char acteristics .............. ............... .............. .............. .......... 56 7.1 serial interface timing ... ................ ................ ................. ................ ................. ............... .. 56 7.2 parallel interface timing ................ ................ ................. ................ ................. ................ .57
list of tables 5 december 9, 2005 table-1 pin description ....... ................ ................. ................ ................. ................ ................ ....... 9 table-2 transmit waveform value for e1 75 ohm................... .............. .............. .............. ....... 16 table-3 transmit waveform value for e1 120 ohm................. .............. .............. .............. ....... 16 table-4 impedance matching for transmitter ...... ................ ................. .............. .............. ......... 17 table-5 impedance matching for receiver .............. .............. ............... .............. .............. ......... 18 table-6 criteria of starting speed adjustment....... ................ ............... .............. .............. ......... 22 table-7 los declare and clear criter ia, adaptive equalizer disabled .. .............. .............. ....... 22 table-8 los declare and clear criter ia, adaptive equalizer enabled ................. .............. ....... 23 table-9 ais condition ......... ................ ................. ................ ................. ................ ................ ..... 23 table-10 criteria for setting/clearing the prbs_s bit ..... ................. ................ ................. ......... 24 table-11 exz definition ........ ................ ................. ................ ................. ................ ............... ...... 27 table-12 interrupt event................. ................. .............. .............. .............. .............. .............. ....... 31 table-13 register list and ma p ................. ................ ................. ................ ................. ............... . 32 table-14 id: device revision register ............... ................. ................ ................. .............. ......... 33 table-15 rst: reset register ... ................ ................ ................. ................ ................. ............... . 33 table-16 gcf: global conf iguration register .... ................. ................ ................. .............. ......... 33 table-17 term: transmit and receive termination configuration regist er ................ .............. 33 table-18 jacf: jitter attenua tion configuration register ................. ................ ................. ......... 34 table-19 tcf0: transmitter configuratio n register 0 ............. ............... .............. .............. ......... 35 table-20 tcf1: transmitter configuratio n register 1 ............. ............... .............. .............. ......... 35 table-21 tcf2: transmitter configuratio n register 2 ............. ............... .............. .............. ......... 35 table-22 tcf3: transmitter configuratio n register 3 ............. ............... .............. .............. ......... 36 table-23 tcf4: transmitter configuratio n register 4 ............. ............... .............. .............. ......... 36 table-24 rcf0: receiver configuration register 0................. ............... .............. .............. ......... 37 table-25 rcf1: receiver configuration register 1................. ............... .............. .............. ......... 37 table-26 rcf2: receiver configuration register 2................. ............... .............. .............. ......... 38 table-27 maint0: maintenance function control register 0..... .............. .............. .............. ....... 39 table-28 maint1: maintenance function control register 1..... .............. .............. .............. ....... 39 table-29 maint6: maintenance function control register 6..... .............. .............. .............. ....... 39 table-30 intm0: interrupt mask register 0 ............... .............. ............... .............. .............. ......... 41 table-31 intm1: interrupt masked regist er 1 ................ ................ ................. ................ ............ 41 table-32 intes: interrupt tr igger edge select register .. ................. ................ ................. ......... 42 table-33 stat0: line status register 0 (real time status m onitor)............ .............. ............ ....... 43 table-34 stat1: line status register 1 (real time status m onitor)............ .............. ............ ....... 44 table-35 ints0: interrupt status regist er 0 ................. .............. .............. .............. .............. ....... 45 table-36 ints1: interrupt status regist er 1 ................. .............. .............. .............. .............. ....... 45 table-37 cnt0: error count er l-byte register 0....... .............. ............... .............. .............. ......... 46 table-38 cnt1: error counter h- byte register 1 ........... ................ ................. ................ ............ 46 table-39 hardware control pin summary .. ............... .............. ............... .............. .............. ......... 47 table-40 absolute maximum rating ........ ................ ................ ............... .............. .............. ......... 49 table-41 recommended operation conditions ................ ................. ................ ................. ......... 49 list of tables
idt82v2051e single channel e1 short haul line interface unit list of tables 6 december 9, 2005 table-42 power consumption.... ................ ................ ................. ................ ................. ................ 50 table-43 dc characteristics ............... ................ .............. .............. ............... .............. ............. ... 50 table-44 receiver electrical characteristics....... ................. ................ ................. .............. ......... 50 table-45 transmitter elec trical characteristics.......... .............. ............... .............. .............. ......... 51 table-46 transmitter and receiver timing char acteristics ............ ................. ................ ............ 52 table-47 jitter tolerance ...... ................ ................. ................ ................. ................ ............... ...... 53 table-48 jitter attenuator char acteristics ........... ................. ................ ................. .............. ......... 5 4 table-49 serial interface timing charac teristics ....... .............. ............... .............. .............. ......... 56 table-50 multiplexed motorola read ti ming characteristics...... .............. .............. .............. ....... 57 table-51 multiplexed motorola write timing characteristics ... ............... .............. .............. ......... 58 table-52 multiplexed intel read timing characteristics .......... ............... .............. .............. ......... 59 table-53 multiplexed intel write timing characteristics .......... ............... .............. .............. ......... 60
list of figures 7 december 9, 2005 figure-1 block diagram ....... ................ ................. ................ ................. ................ ................ ........ 2 figure-2 idt82v2051e tqfp44 package pin assignment ........ .............. .............. ............ .......... 8 figure-3 e1 waveform template diagram ............... .............. ............... .............. .............. .......... 15 figure-4 e1 pulse template test circuit .............. ................ ................. .............. .............. .......... 15 figure-5 receive monitor gain adaptive equalizer ................ ............... .............. .............. .......... 18 figure-6 transmit/receive line circuit .. ................ ................ ............... .............. .............. .......... 18 figure-7 monitoring receive line in anot her chip ................. ............... .............. .............. .......... 19 figure-8 monitor transmit line in another chip ..... ................ ............... .............. .............. .......... 19 figure-9 jitter attenuator ... ................ ................ ................. ................ ................. ................ ........ 21 figure-10 los declare and clear ......... ................. .............. .............. .............. .............. .............. .22 figure-11 analog loopback ......... ................ ................. ................ ................. .............. ............. .... 25 figure-12 digital loopback .... ................ ................. ................ ................. ................ ............... ....... 25 figure-13 remote loopback ...... ................ ................ ................. ................ ................. .............. ... 26 figure-14 auto report mode ............... ................ .............. .............. ............... .............. ............. .... 27 figure-15 manual report mode ................ .............. .............. .............. .............. .............. ............. .. 28 figure-16 tclk operation flowchart .... ................. ................ .............. .............. .............. ............. 2 9 figure-17 serial microcontroller interf ace function timing ...... ............... .............. .............. .......... 30 figure-18 transmit system interface ti ming .................. ................ ................. ................ ............. 52 figure-19 receive system interface timi ng .............. .............. ............... .............. .............. .......... 53 figure-20 e1 jitter tolerance performanc e ............... .............. ............... .............. .............. .......... 54 figure-21 e1 jitter transfer performance ........... ................. ................ ................. .............. .......... 55 figure-22 serial interface write timing ............... ................. .............. .............. .............. .............. .56 figure-23 serial interface read timing with sclke=1 ........... ............... .............. .............. .......... 56 figure-24 serial interface read timing with sclke=0 ........... ............... .............. .............. .......... 56 figure-25 multiplexed motorola read ti ming ............. .............. ............... .............. .............. .......... 57 figure-26 multiplexed motorola write ti ming .................. ................ ................. ................ ............. 58 figure-27 multiplexed intel read timing ................ ................ .............. .............. .............. ............. 5 9 figure-28 multiplexed intel write timing ................ ................ .............. .............. .............. ............. 60 list of figures
idt82v2051e single channel e1 short haul line interface unit idt82v2051e pin configurations 8 december 9, 2005 1 idt82v2051e pin configurations figure-2 idt82v2051e tqfp 44 package pin assignment tclk tdp / td tdn rclk rdp / rd rdn / cv los vddd mclk gndd rclke idt82v2051e 1 2 3 4 5 6 7 8 9 10 11 14 12 13 15 18 16 17 19 22 20 21 44 41 43 42 40 37 39 38 36 35 34 ad7 ad6 ad5 ad4 / puls ad3 ad2 / rpd ad1 / patt1 ad0 / patt0 ale / as / sclk/ lp1 wr / r/ w / sdi / lp0 rdy / ack / sdo / term ic vddt tring ttip gndt gnda rring rtip vdda ref ic 33 32 31 30 29 28 27 26 25 24 23 rd / ds / sclke / mont cs / rxtxm1 int / rxtxm0 vddio gndio mode1 mode0 ja1 ja0 thz rst
idt82v2051e single channel e1 short haul line interface unit pin description 9 december 9, 2005 notes: 1. tclk missing: the state of tclk continues to be high level or low level over 70 mclk cycles. 2 pin description table-1 pin description name type pin no. description ttip tring analog output 37 36 ttip/tring: transmit bipolar tip/ring these pins are the differential line driver outputs. they will be in high impedance state under the following conditions: ? thz pin is high; ? thz bit is set to 1; ? loss of mclk; ? loss of tclk (exceptions: remote loopback; transmit internal pattern by mclk); ? transmit path power down; ? after software reset; pin reset and power on. rtip rring analog input 41 40 rtip/rring: receive bipolar tip/ring these signals are the differential receiver inputs. td/tdp tdn i2 3 td: transmit data when the device is in single rail mode, the nrz data to be transmitted is input on this pin. data on td pin is sampled into the device on the active edge of tclk and is encoded by ami or hdb3 line code rules before being transmitted. in this mode, tdn should be connected to ground. tdp/tdn: positive/negative transmit data when the device is in dual rail mode, the nrz data to be transmitted for positive/negative pulse is input on these pins. data on tdp/tdn pin is sampled into the device on the active edge of tclk. the line code in dual rail mode is as follows: tclk i 1 tclk: transmit clock input this pin inputs a 2.048 mhz transmit clock. the transmit data at td/tdp or tdn is sampled into the device on the active edge of tclk. if tclk is missing 1 and the tclk missing interrupt is not masked, an interrupt will be generated. rd/rdp cv/rdn o5 6 rd: receive data output in single rail mode, this pin outputs nrz data. the data is decoded according to ami or hdb3 line code rules. cv: code violation indication in single rail mode, the bpv/cv code violation will be repo rted by driving the cv pin to high level for a full clock cycle. hdb 3 line code violation can be indicated if the hdb3 decoder is enabled. when ami decoder is selected, bipolar violation will be in di- cated. in hardware control mode, the exz, bpv/cv er rors in received data stre am are always monitored by the cv pin if single rail mode is chosen. rdp/rdn: positive/negative receive data output in dual rail mode, this pin outputs the re-timed nrz data when cdr is enabled, or directly outputs the raw rz slicer data if cd r is bypassed. active edge and level select: data on rdp/rdn or rd is clocked with either the rising or the falling edge of rclk. the active polarity is also selectable. rclk o 4 rclk: receive clock output this pin outputs a 2.048 mhz receive clock. under los condition with ais enabled (bit aise=1), rclk is derived from mclk. in clock recovery mode, this signal provides the clock recove red from the rtip/rring signal. the receive data (rd in single rail mode or rdp and rdn in dual rail mode) is clocked out of the device on the active edge of rclk. if clock recovery is bypassed, rclk is the exclusive or (xor) output of the dual rail slicer data rdp and rdn. this signal can be used in appli- cations with external clock recovery circuitry. tdp tdn output pulse 0 0 space 0 1 positive pulse 1 0 negative pulse 1 1 space
idt82v2051e single channel e1 short haul line interface unit pin description 10 december 9, 2005 mclk i 9 mclk: master clock input a built-in clock system that accepts a 2.048mhz reference clock. this reference clock is used to generate several internal ref- erence signals: ? timing reference for the integrated clock recovery unit. ? timing reference for the integrated digital jitter attenuator. ? timing reference for microcontroller interface. ? generation of rclk signal during a loss of signal condition. ? reference clock to transmit all ones, all zeros and prbs pattern. note that for atao and ais, mclk is always used as the reference clock. ? reference clock during the transmit all ones (tao) condition or sending prbs in hardware control mode. the loss of mclk will turn ttip/tring into high impedance status. los o 7 los: loss of signal output this is an active high signal used to indicate the loss of received signal. when los pin becomes high, it indicates the loss of received signal. the los pin will become low automatically when valid received signal is detected again. the criteria of loss of signal are described in 3.5 los and ais detection . ref i 43 ref: reference resister an external resistor (3 k ? , 1%) is used to connect this pin to ground to provide a standard reference current for internal circuit. mode1 mode0 i17 16 mode[1:0]: operation mode of control interface select the level on this pin determines which control mode is used to control the device as follows: ? the serial microcontroller interface consists of cs , sclk, sclke, sdi, sdo and int pins. sclke is used for the selection of the active edge of sclk. ? the parallel multiplexed microcontroller interface consists of cs , ad[7:0], ds / rd , r/ w / wr , ale/as, ack /rdy and int pins. (refer to 3.11 microcontroller interfaces for details) ? hardware interface consists of puls, thz, rclke, lp[1:0 ], patt[1:0], ja[1:0], mont, term, rpd, mode[1:0] and rxtxm[1:0] rclke i 11 rclke: the active edge of rclk select in hardware control mode, this pin selects the active edge of rclk ? l= select the rising edge as the active edge of rclk ? h= select the falling edge as the active edge of rclk in software control mode, this pin should be connected to gndio. cs rxtxm1 i21 cs : chip select in serial or parallel microcontroller interface mode, this is the active low enable signal. a low level on this pin enables ser ial or parallel microcontroller interface. rxtxm[1:0]: receive and transmit path operation mode select in hardware control mode, these pins are used to select the single rail or dual rail operation modes as well as ami or hdb3 lin e coding: ? 00= single rail with hdb3 coding ? 01= single rail with ami coding ? 10= dual rail interface with cdr enabled ? 11= slicer mode (dual rail interface with cdr disabled) table-1 pin description (continued) name type pin no. description mode[1:0] control interface mode 00 hardware interface 01 serial microcontroller interface 10 parallel ?multiplexed -motorola interface 11 parallel ?multiplexed -intel interface
idt82v2051e single channel e1 short haul line interface unit pin description 11 december 9, 2005 int rxtxm0 o i 20 int : interrupt request in software control mode, this pin outputs the general interrupt request for all interrupt sources. these interrupt sources can be masked individually via registers ( intm0, 14h ) and ( intm1, 15h ). the interrupt status is reported via the registers ( ints0, 19h ) and ( ints1, 1ah ). output characteristics of this pin can be defined to be push-pull (active high or active low) or open-drain (active low) by set ting int_pin[1:0] ( gcf, 02h ). rxtxm0 see rxtxm1 above. sclk ale as lp1 i 25 sclk: shift clock in serial microcontroller interface mode, this signal is the shift clock for the serial interface. configuration data on sdi pi n is sam- pled on the rising edge of sclk. configuration and status data on sdo pin is clocked out of the device on the falling edge of sclk if sclke pin is high, or on the rising edge of sclk if sclke pin is low. ale: address latch enable in parallel microcontroller interface mode with multiplexed intel interface, the address on ad[7:0] is sampled into the device on the falling edge of ale. as: address strobe in parallel microcontroller interface mode with multiplexed motorola interface, the address on ad[7:0] is latched into the devi ce on the falling edge of as. lp[1:0]: loopback mode select when the chip is configured by hardware, this pin is used to select loopback operation modes: ? 00= no loopback ? 01= analog loopback ? 10= digital loopback ? 11= remote loopback sdi wr r/ w lp0 i 24 sdi: serial data input in serial microcontroller interface mode, this signal is the input data to the serial interface. configuration data at sdi pin is sam- pled by the device on the rising edge of sclk. wr : write strobe in intel parallel multiplexed interface mode, this pin is asserted low by the microcontroller to initiate a write cycle. the da ta on ad[7:0] is sampled into the device in a write operation. r/ w : read/write select in motorola parallel multiplexed interface mode, this pin is low for write operation and high for read operation. lp0 see lp1 above. table-1 pin description (continued) name type pin no. description
idt82v2051e single channel e1 short haul line interface unit pin description 12 december 9, 2005 sdo ack rdy term o i 23 sdo: serial data output in serial microcontroller interface mode, this signal is the output data of the serial interface. configuration or status data at sdo pin is clocked out of the device on the falling edge of sclk if sclke pin is high, or on the rising edge of sclk if sclke pin is low. ack : acknowledge output in motorola parallel mode interface, the low level on this pin means: ? the valid information is on the data bus during a read operation. ? the write data has been accepted during a write cycle. rdy: ready signal output in intel parallel mode interface, the low level on this pin means a read or write operation is in progress; a high acknowledges a read or write operation has been completed. term: internal or external termin ation select in hardware mode this pin selects internal or external impedance matching for both receiver and transmitter. ? 0 = ternary interface with external impedance matching network ? 1 = ternary interface with internal impedance matching network sclke rd ds mont i 22 sclke: serial clock edge select in serial microcontroller interface mode, this signal selects the active edge of sclk for outputting sdo. the output data is va lid after some delay from the active clock edge. it can be sampled on the opposite edge of the clock. the active clock edge which clocks the data out of the device is selected as shown below: rd : read strobe in intel parallel multiplexed interface mode, the data is driven to ad[7:0] by the device during low level of rd in a read operation. ds : data strobe in motorola parallel multiplexed interface mode, this signal is the data strobe of the parallel interface. in a write operation (r/ w = 0), the data on ad[7:0] is sampled into the device. in a read operation (r/ w = 1), the data is driven to ad[7:0] by the device. mont: receive monitor gain select in hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver: 0= 0 db 1= 26 db ad7 i/o 33 ad7: address/data bus bit7 in intel/motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontro ller interface. in serial microcontroller interface mode, this pin should be connected to ground through a 10 k ? resistor. in hardware mode, this pin has to be tied to gnd. ad6 i/o 32 ad6: address/data bus bit6 in intel/motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontro ller interface. in serial microcontroller interface mode, this pin should be connected to ground through a 10 k ? resistor. in hardware mode, this pin has to be tied to gnd. table-1 pin description (continued) name type pin no. description sclke sclk low rising edge is the active edge. high falling edge is the active edge.
idt82v2051e single channel e1 short haul line interface unit pin description 13 december 9, 2005 ad5 i/o 31 ad5: address/data bus bit5 in intel/motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontro ller interface. in serial microcontroller interface mode, this pin should be connected to ground through a 10 k ? resistor. in hardware mode, this pin has to be tied to gnd. ad4 i/o 30 ad4: address/data bus bit4 in intel/motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontro ller interface. in serial microcontroller interface mode, this pin should be connected to ground through a 10 k ? resistor. puls: this pin is used to select the following functions in hardware control mode: ? transmit pulse template ? internal termination impedance (75 ? / 120 ? ) refer to 5 hardware control pin summary for details. ad3 i/o 29 ad3: address/data bus bit3 in intel/motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontro ller interface. in serial microcontroller interface mode, this pin should be connected to ground through a 10 k ? resistor. ad2 rpd i/o i 28 ad2: address/data bus bit2 in intel/motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontro ller interface. in serial microcontroller interface mode, this pin should be connected to ground through a 10 k ? resistor. rpd: receiver power down cont rol in hardware control mode ? 0= normal operation ? 1= receiver power down ad1 patt1 i/o i 27 ad1: address/data bus bit1 in intel/motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontro ller interface. in serial microcontroller interface mode, this pin should be connected to ground through a 10 k ? resistor. patt[1:0]: transmit pattern select in hardware control mode, this pin selects the transmit pattern ? 00 = normal ? 01= all ones ? 10= prbs ? 11= transmitter power down ad0 patt0 i/o i 26 ad0: address/data bus bit0 in intel/motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontro ller interface. in serial microcontroller interface mode, this pin should be connected to ground through a 10 k ? resistor. see above. ja1 i 15 ja[1:0]: jitter attenuation position, bandwidth and the depth of fifo select (only used for hardware control mode) ? 00 = ja is disabled ? 01 = ja in receiver, broad bandwidth, fifo=64 bits ? 10 = ja in receiver, narrow bandwidth, fifo=128 bits ? 11 = ja in transmitter, narrow bandwidth, fifo=128 bits in software control mode, this pin should be connected to ground. ja0 i 14 see above. table-1 pin description (continued) name type pin no. description
idt82v2051e single channel e1 short haul line interface unit pin description 14 december 9, 2005 rst i12 rst : hardware reset the chip is forced to reset state if a low signal is input on this pin for more than 100 ns. mclk must be active during reset. thz i 13 thz: transmitter driver high impedance enable this signal enables or disables transmitter driver. a low level on this pin enables the driver while a high level on this pin p laces driver in high impedance state. note that the functionality of the internal circuits is not affected by this signal. power supplies and grounds vddio - 19 3.3 v i/o power supply gndio - 18 i/o ground vddt - 35 3.3 v power supply for transmitter driver gndt - 38 analog ground for transmitter driver vdda - 42 3.3 v analog core power supply gnda - 39 analog core ground vddd - 8 digital core power supply gndd - 10 digital core ground others ic - 34 ic: internal connection internal use. this pin should be left open when in normal operation. ic - 44 ic: internal connection internal use. this pin should be connected to ground when in normal operation. table-1 pin description (continued) name type pin no. description
idt82v2051e single channel e1 short haul line interface unit functional description 15 december 9, 2005 3 functional description 3.1 control mode selection the idt82v2051e can be configured by software or by hardware. the software control mode supports serial control interface, motorola multi- plexed control interface and intel multiplexed control interface. the con- trol mode is selected by mode1 and mode0 pins as follows: ? the serial microcontroller interface consists of cs , sclk, sclke, sdi, sdo and int pins. sclke is used for the selection of active edge of sclk. ? the parallel multiplexed microcontroller interface consists of cs , ad[7:0], ds / rd , r/ w / wr , ale/as, ack /rdy and int pins. ? hardware interface consists of puls, thz, rclke, lp[1:0], patt[1:0], ja[1:0], mont, term, rpd, mode[1:0] and rxtxm[1:0]. refer to 5 hardware control pin summary for details about hardware control. 3.2 transmit path the transmit path of idt82v2051e c onsists of an encoder, an optional jitter attenuator, a waveform shaper , a line driver and a programmable transmit termination. 3.2.1 transmit path system interface the transmit path system interface c onsists of tclk pin, td/tdp pin and tdn pin. tclk is a 2.048 mhz clock. if tclk is missing for more than 70 mclk cycles, an interrupt will be generated if it is not masked. transmit data is sampled on the td /tdp and tdn pins by the active edge of tclk. the active edge of tclk can be selected by the tclk_sel bit ( tcf0, 05h ). and the active level of the data on td/tdp and tdn can be selected by the td_inv bit ( tcf0, 05h ). in hardware control mode, the falling edge of tclk and the active high of transmit data are always used. the transmit data from the system si de can be provided in two different ways: single rail and dual rail. in si ngle rail mode, only td pin is used for transmitting data and the t_md[1] bit ( tcf0, 05h ) should be set to ?0?. in dual rail mode, both tdp pin a nd tdn pin are used for transmitting data, the t_md[1] bit ( tcf0, 05h ) should be set to ?1?. 3.2.2 encoder in single rail mode, the encoder can be configured to be a hdb3 encoder or an ami encoder by setting t_md[0] bit ( tcf0, 05h ). in dual rail mode, the encoder is by -passed. in dual rail mode, a logic ?1? on the tdp pin and a logic ?0? on the tdn pin results in a negative pulse on the ttip/tring; a logic ?0? on tdp pin and a logic ?1? on tdn pin results in a positive pulse on the ttip/tring. if both tdp and tdn are high or low, the ttip/tring outputs a space (refer to td/tdp, tdn pin description ). in hardware control mode, the operation mode of receive and transmit path can be selected by setting rxtxm1 and rxtxm0 pins. refer to 5 hardware control pin summary for details. 3.2.3 pulse shaper the idt82v2051e provides two ways of manipulating the pulse shape before sending it. one is to use preset pulse templates, the other is to use user-programmable arbitrary waveform template. in software control mode, the pulse shape can be selected by setting the related registers. in hardware control mode, the pulse shape can be selected by setting puls pin. refer to 5 hardware control pin summary for details. 3.2.3.1 preset pulse templates the pulse shape is shown in figure-3 according to the g.703 and the measuring diagram is shown in figure-4 . in internal impedance matching mode, if the cable impedance is 75 ? , the puls[3:0] bits ( tcf1, 06h ) should be set to ?0000?; if the cable impedance is 120 ? , the puls[3:0] bits ( tcf1, 06h ) should be set to ?0001?. in external impedance matching mode, for both e1/75 ? and e1/120 ? cable impedance, puls[3:0] should be set to ?0001?. figure-3 e1 waveform template diagram figure-4 e1 pulse template test circuit control interface mode 00 hardware interface 01 serial microcontroller interface. 10 parallel ?multiplexed -motorola interface 11 parallel ?multiplexed -intel interface -0.6 -0.4 -0.2 0 0.2 0.4 0.6 -0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20 tim e in u nit intervals normalized amplitude idt82v2051e v out r load ttip tring note: 1. for r load = 75 ? (nom), v out (peak) = 2.37 v (nom) 2. for r load = 120 ? (nom), v out (peak) = 3.00 v (nom)
idt82v2051e single channel e1 short haul line interface unit functional description 16 december 9, 2005 3.2.3.2 user-programmable arbitrary waveform when the puls[3:0] bits are set to ?11xx?, user-progr ammable arbitrary waveform generator mode can be used. this allows the transmitter perfor- mance to be tuned for a wide variety of line condition or special application. each pulse shape can extend up to 4 uis (unit interval), addressed by ui[1:0] bits ( tcf3, 08h ) and each ui is divided into 16 sub-phases, addressed by the samp[3:0] bits ( tcf3, 08h ). the pulse amplitude of each phase is represented by a binary byte, within the range from +63 to -63, stored in wdat[6:0] bits ( tcf4, 09h ) in signed magnitude form. the most positive number +63 (d) represents t he positive maximum amplitude of the transmit pulse while the most negativ e number -63 (d) represents the max- imum negative amplitude of the transmi t pulse. therefore, up to 64 bytes are used. there are two standard templates which are stored in an on-chip rom. user can select one of them as reference and make some changes to get the desired waveform. user can change the wave shape and the amplitude to get the desired pulse shape. in order to do this, firstl y, users can choose a set of waveform value from the following two tables, wh ich is the most similar to the desired pulse shape. table-2 and table-3 list the sample data and scaling data of each of the two templates. then modify the corresponding sample data to get the desired transmit pulse shape. secondly, through the value of scal[5:0] bits increased or decreased by 1, the pulse amplitude can be scal ed up or down at the percentage ratio against the standard pulse amplitude if needed. for different pulse shapes, the value of scal[5:0] bits and the scaling percentage ra tio are different. the following two tables list these values. do the followings step by step, the desired waveform can be pro- grammed, based on the selected waveform template: (1).select the ui by ui[1:0] bits ( tcf3, 08h ) (2).specify the sample address in the selected ui by samp [3:0] bits ( tcf3, 08h ) (3).write sample data to wdat[6:0] bits ( tcf4, 09h ). it contains the data to be stored in the ram, addressed by the selected ui and the corresponding sample address. (4).set the rw bit ( tcf3, 08h ) to ?0? to implement writing data to ram, or to ?1? to implement read data from ram (5).implement the read from ram/write to ram by setting the done bit ( tcf3, 08h ) repeat the above steps until all the sample data are written to or read from the internal ram. (6).write the scaling data to scal[5:0] bits ( tcf2, 07h ) to scale the amplitude of the waveform based on the selected standard pulse amplitude when more than one ui is used to compose the pulse template, the over- lap of two consecutive pulses coul d make the pulse amplitude overflow (exceed the maximum limitation) if t he pulse amplitude is not set properly. this overflow is captured by dac_ov_is bit ( ints1, 1ah ), and, if enabled by the dac_ov_im bit ( intm1, 15h ), an interrupt will be generated. the following tables give all the sample data based on the preset pulse templates in detail for reference. for preset pulse templates, scaling up/ down against the pulse amplitude is not supported. 1. table-2 transmit waveform value for e1 75 ? 2. table-3 transmit waveform value for e1 120 ? table-2 transmit waveform value for e1 75 ohm sample ui 1 ui 2 ui 3 ui 4 1 0000000 0000000 0000000 0000000 2 0000000 0000000 0000000 0000000 3 0000000 0000000 0000000 0000000 4 0001100 0000000 0000000 0000000 5 0110000 0000000 0000000 0000000 6 0110000 0000000 0000000 0000000 7 0110000 0000000 0000000 0000000 8 0110000 0000000 0000000 0000000 9 0110000 0000000 0000000 0000000 10 0110000 0000000 0000000 0000000 11 0110000 0000000 0000000 0000000 12 0110000 0000000 0000000 0000000 13 0000000 0000000 0000000 0000000 14 0000000 0000000 0000000 0000000 15 0000000 0000000 0000000 0000000 16 0000000 0000000 0000000 0000000 scal[5:0] = 100001 (default), one step change of this value of scal[5:0] results in 3% scaling up/down against the pulse amplitude. table-3 transmit waveform value for e1 120 ohm sample ui 1 ui 2 ui 3 ui 4 1 0000000 0000000 0000000 0000000 2 0000000 0000000 0000000 0000000 3 0000000 0000000 0000000 0000000 4 0001111 0000000 0000000 0000000 5 0111100 0000000 0000000 0000000 6 0111100 0000000 0000000 0000000 7 0111100 0000000 0000000 0000000 8 0111100 0000000 0000000 0000000 9 0111100 0000000 0000000 0000000 10 0111100 0000000 0000000 0000000 11 0111100 0000000 0000000 0000000 12 0111100 0000000 0000000 0000000 13 0000000 0000000 0000000 0000000 14 0000000 0000000 0000000 0000000 15 0000000 0000000 0000000 0000000 16 0000000 0000000 0000000 0000000 scal[5:0] = 100001 (default), one step change of this value of scal[5:0] results in 3% scaling up/down against the pulse amplitude.
idt82v2051e single channel e1 short haul line interface unit functional description 17 december 9, 2005 3.2.4 transmit path line interface the transmit line interface consists of ttip pin and tring pin. the impedance matching can be realized by the internal impedance matching circuit or the external impedance matc hing circuit. if t_term[2] is set to ?0?, the internal impedance matching circ uit will be selected. in this case, the t_term[1:0] bits ( term, 03h ) can be set to choose 75 ? or 120 ? internal impedance of ttip/tring. if t_term[2] is set to ?1?, the internal impedance matching circuit w ill be disabled. in this case, the external impedance matching circuit will be used to realize the impedance matching. figure-6 shows the appropriate external components to connect with the cable. table-4 is the list of the recommended impedance matching for transmitter. in hardware control mode, term pin can be used to select impedance matching for both receiver and transmitter. if term pin is low, external impedance network will be used for impedance matching. if term pin is high, internal impedance will be used for impedance matching and puls pin will be set to select the specific internal impedance. refer to 5 hardware control pin summary for details. the ttip/tring pins can also be turned into high impedance by setting the thz bit ( tcf1, 06h ) to ?1?. in this state, the internal transmit circuits are still active. in hardware control mode, ttip/tring can be turned into high imped- ance by pulling thz pin to high. refer to 5 hardware control pin summary for details. besides, in the following cases, bot h ttip/tring pins will also become high impedance: ? loss of mclk; ? loss of tclk (exceptions: re mote loopback; transmit internal pattern by mclk); ? transmit path power down; ? after software reset; pin reset and power on. note : the precision of the resistors should be better than 1% 3.2.5 transmit path power down the transmit path can be powered down by setting the t_off bit ( tcf0, 05h ) to ?1?. in this case, the ttip/t ring pins are turned into high imped- ance. in hardware control mode, the transmit path can be powered down by pulling both patt1 and patt0 pins to high. refer to 5 hardware control pin summary for details. table-4 impedance matching for transmitter cable configuration internal termination external termination t_term[2:0] puls[3:0] r t t_term[2:0] puls[3:0] r t e1 / 75 ? 000 0000 0 ? 1xx 0001 9.4 ? e1 / 120 ? 001 0001
idt82v2051e single channel e1 short haul line interface unit functional description 18 december 9, 2005 3.3 receive path the receive path consists of receiv e internal termination, monitor gain, amplitude/wave shape detector, digital tuning controller, adaptive equalizer, data slicer, cdr (clock & data recovery), optional jitter attenuator, decoder and los/ais detector. refer to figure-5 . 3.3.1 receive internal termination the impedance matching can be real ized by the internal impedance matching circuit or the external impedance matching circuit. if r_term[2] is set to ?0?, the internal impedance ma tching circuit will be selected. in this case, the r_term[1:0] bits ( term, 03h ) can be set to choose 75 ? or 120 ? internal impedance of rtip/rring. if r_term[2] is set to ?1?, the inter- nal impedance matching circuit will be di sabled. in this case, the external impedance matching circuit will be us ed to realize the impedance matching. figure-6 shows the appropriate external components to connect with the cable. table-5 is the list of the recommended impedance matching for receiver. figure-5 receive monitor gain adaptive equalizer figure-6 transmit/receive line circuit table-5 impedance matching for receiver cable configuration internal te rmination external termination r_term[2:0] r r r_term[2:0] r r e1/75 ? 000 120 ? 1xx 75 ? e1/120 ? 001 120 ? adaptive equalizer/ monitor gain los/ais detector data slicer decoder los rclk rdp rdn rtip clock and data recovery receive internal termination rring jitter attenuator a b ? ? ?? r x line r r ? ? t x line r t r t rtip rring tring ttip idt82v2051e vddt vddt d4 d3 d2 d1 1 : 1 2 : 1 d6 d5 d8 d7 cp vdda vdda ? 0.1 f gndt vddt 68 f 1 3.3 v ? 0.1 f gnda vdda 68 f 3.3 v 1 ? ? ? ?
idt82v2051e single channel e1 short haul line interface unit functional description 19 december 9, 2005 in hardware control mode, term and puls pins can be used to select impedance matching for both receiver and transmitter. if term pin is low, external impedance network will be used for impedance matching. if term pin is high, internal impedance w ill be used for impedance matching and puls pins can be set to select the specific internal impedance. refer to 5 hardware control pin summary for details. 3.3.2 line monitor the non-intrusive monitoring on channel s located in other chips can be performed by tapping the monito red channel through a high impedance bridging circuit. refer to figure-7 and figure-9 . after a high resistance bridging circui t, the signal arriving at the rtip/ rring is dramatically attenuated. to compensate this attenuation, the monitor gain can be used to boost the signal by 22 db, 26 db and 32 db, selected by mg[1:0] bits ( rcf2, 0ch ). for normal operation, the monitor gain should be set to 0 db. in hardware control mode, mont pin can be used to set the monitor gain. when mont pin is low, the monitor gain is 0 db. when mont pin is high, the monitor gain is 26 db. refer to 5 hardware control pin summary for details. note that los indication is not supported if the device is operated in line monitor mode figure-7 monitoring receive line in another chip figure-8 monitor transmit line in another chip rtip rring rtip rring normal receive mode monitor mode dsx cross connect point r monitor gain =22/26/32db monitor gain=0db ttip tring rtip rring normal transmit mode monitor mode dsx cross connect point r monitor gain monitor gain =22/26/32db
idt82v2051e single channel e1 short haul line interface unit functional description 20 december 9, 2005 3.3.3 adaptive equalizer the adaptive equalizer can be enabled to increase the receive sensi- tivity and to allow programming of the los level up to -24 db. see3.5 los and ais detection. it can be enabled or disabled by setting eq_on bit to ?1? or ?0? ( rcf1, 0bh ). 3.3.4 receive sensitivity the receive sensitivity is -10 db . with the adaptive equalizer enabled, the receive sensitivity will be -20 db. in hardware mode, the adaptive equalizer can not be enabled and the receive sensitivity is fixed at -10 db. refer to 5 hardware control pin sum- mary for details. 3.3.5 data slicer the data slicer is used to generate a standard amplitude mark or a space according to the amplitude of the input signals. the threshold can be 40%, 50%, 60% or 70%, as selected by the slice[1:0] bits ( rcf2, 0ch ). the output of the data slicer is fo rwarded to the cdr (clock & data recov- ery) unit or to the rdp/rdn pins directly if the cdr is disabled. 3.3.6 cdr (clock & data recovery) the cdr is used to recover the cl ock and data from the received signal. the recovered clock tracks the jitter in the data output from the data slicer and keeps the phase relationship between data and clock during the absence of the incoming pulse. the cdr can also be by-passed in the dual rail mode. when cdr is by-passed, the data from the data slicer is output to the rdp/rdn pins directly. 3.3.7 decoder the r_md[1:0] bits ( rcf0, 0ah ) are used to select the ami decoder or hdb3 decoder. when the chip is configured by hardw are, the operation mode of receive and transmit path can be selected by setting rxtxm1 and rxtxm0 pins. refer to 5 hardware control pin summary for details.
idt82v2051e single channel e1 short haul line interface unit functional description 21 december 9, 2005 3.3.8 receive path system interface the receive path system interface co nsists of rclk pin, rd/rdp pin and rdn pin. the rclk outputs a recovered 2.048 mhz clock. the received data is updated on the rd/rdp and rdn pins on the active edge of rclk. the active edge of rclk can be selected by the rclk_sel bit ( rcf0, 0ah ). and the active level of the data on rd/rdp and rdn can be selected by the rd_inv bit ( rcf0, 0ah ). in hardware control mode, only the active edge of rclk can be selected. if rclke is set to high, the falling edge will be chosen as the active edge of rclk. if rclke is set to low, the rising edge will be chosen as the active edge of rclk. the active level of the data on rd/rdp and rdn is the same as that in software control mode. the received data can be output to the system side in two different ways: single rail or dual rail, as selected by r_md bit [1] ( rcf0, 0ah ). in single rail mode, only rd pin is used to output data and the rdn/cv pin is used to report the received errors. in dual rail mode, both rdp pin and rdn pin are used for outputting data. in the receive dual rail mode, t he cdr unit can be by-passed by setting r_md[1:0] to ?11? (binary). in this situation, the output data from the data slicer will be output to the rdp/r dn pins directly, and the rclk outputs the exclusive or (xor) of the rdp and rdn. this is called receiver slicer mode. in this case, the transmit path is still operating in dual rail mode. 3.3.9 receive path power down the receive path can be powered down by setting r_off bit ( rcf0, 0ah ) to ?1?. in this case, the rclk, rd/rdp, rdn and los will be logic low. in hardware control mode, receiver power down can be selected by pull- ing rpd pin to high. refer to 5 hardware control pin summary for more details. 3.4 jitter attenuator there is one jitter attenuator in the idt82v2051e. the jitter attenuator can be deployed in the transmit path or the receive path, and can also be disabled. this is selected by the jacf[1:0] bits ( jacf, 04h ). in hardware control mode, jitter attenuator position, bandwidth and the depth of fifo can be selected by ja[1:0] pins. refer to 5 hardware control pin summary for details. 3.4.1 jitter attenuation function descripton the jitter attenuator is composed of a fifo and a dpll, as shown in figure-9 . the fifo is used as a pool to buffer the jittered input data, then the data is clocked out of the fifo by a de-jittered clock. the depth of the fifo can be 32 bits, 64 bits or 128 bi ts, as selected by the jadp[1:0] bits ( jacf, 04h ). in hardware control mode, the depth of fifo can be selected by ja[1:0] pins. refer to 5 hardware control pin summary for details. con- sequently, the constant delay of the jitter attenuator will be 16 bits, 32 bits or 64 bits. deeper fifo can tolerate larger jitter, but at the cost of increasing data latency time. figure-9 jitter attenuator the corner frequency of the dpll can be 0.9 hz or 6.8 hz, as selected by the jabw bit ( jacf, 04h ). the lower the corner frequency is, the longer time is needed to achieve synchronization. when the incoming data moves faster than the outgoing data, the fifo will overflow. this overflow is captured by the jaov_is bit ( ints1, 1ah ). if the incoming data moves slower than the outgoing data, the fifo will underflow. this underflow is captured by the jaud_is bit ( ints1, 1ah ). for some applications that are sensitive to data corruption, the ja limit mode can be enabled by setting ja_limit bit ( jacf, 04h ) to ?1?. in the ja limit mode, the speed of the outgoing data wi ll be adjusted automatically when the fifo is close to its full or empti ness. the criteria of starting speed adjust- ment are shown in table-6 . the ja limit mode can reduce the possibility of fifo overflow and underflow, but the qual ity of jitter attenuation is deteri- orated. fifo 32/64/128 dpll jittered data de-jittered data jittered clock de-jittered clock mclk w r rclk rd/rdp rdn
idt82v2051e single channel e1 short haul line interface unit functional description 22 december 9, 2005 3.4.2 jitter attenuator performance the performance of the jitter attenuat or in the idt82v2051e meets the itu-t i.431, g.703, g.736-739, g.823, g.824, etsi 300011 and etsi tbr12/13 specifications. details of the jitter attenuator performance is shown in table-47 jitter tolerance and table-48 jitter attenuator charac- teristics . 3.5 los and ai s detection 3.5.1 los detection the loss of signal detector monitors the amplitude of the incoming sig- nal level and pulse density of the received signal on rtip and rring. ? los declare (los=1) a los is detected when the incoming signal has ?no transitions?, i.e., when the signal level is less than q db below nominal for n consecutive pulse intervals. here n is defined by lac bit ( maint0, 0dh ). los will be declared by pulling los pin to high (los=1) and los interrupt will be gen- erated if it is not masked. note that los indication is not supported if the device is operated in line monitor mode. refer to 3.3.2 line monitor . ? los clear (los=0) the los is cleared when the incoming signal has ?transitions?, i.e., when the signal level is greater than p db below nominal and has an aver- age pulse density of at least 12.5% for m consecutive pulse intervals, start- ing with the receipt of a pulse. here m is defined by lac bit ( maint0, 0dh ). los status is cleared by pulling los pin to low. figure-10 los declare and clear ? los detect level threshold with the adaptive equalizer off, t he amplitude threshold q is fixed on 800 mvpp, while p=q+200 mvpp (200 mvpp is the los level detect hys- teresis). with the adaptive equalizer on, the value of q can be selected by los[4:0] bit ( rcf1, 0bh ), while p=q+4 db (4 db is the los level detect hysteresis). refer to table-20 tcf1: transmitter configuration register 1 for los[4:0] bit values available. when the chip is configured by hardware, the adaptive equalizer can not be enabled and programmable los leve ls are not available (pin 29 has to be set to ?0?). ? criteria for declare and clear of a los detect the detection supports g.775 and etsi 300233/i.431. the criteria can be selected by lac bit ( maint0, 0dh ). table-7 and table-8 summarize los declare and clear criteria for both with and without the adaptive equalizer enabled. ? all ones output during los on the system side, the rdp/rdn will reflect the input pulse ?transition? at the rtip/rring side and output recovered clock (but the quality of the output clock can not be guaranteed when the input level is lower than the maximum receive sensitivity) when aise bit ( maint0, 0dh ) is 0; or output all ones as ais when aise bit ( maint0, 0dh ) is 1. in this case, rclk out- put is replaced by mclk. on the line side, the ttip/tring will output all ones as ais when atao bit ( maint0, 0dh ) is 1. the all ones pattern uses mclk as the reference clock. los indicator is always active for all kinds of loopback modes. table-6 criteria of starting speed adjustment fifo depth criteria for adjusting data outgoing speed 32 bits 2 bits close to its full or emptiness 64 bits 3 bits close to its full or emptiness 128 bits 4 bits close to its full or emptiness signal levelp density=ok los=1 los=0 table-7 los declare and clear criteria, adaptive equalizer disabled control bit (lac) los declare threshold los clear threshold 0 = g.775 level < 800 mvpp; n=32 bits level > 1 vpp; m=32 bits; 12.5% mark density; <16 consecutive zeroes 1 = i.431/etsi level < 800 mvpp; n=2048 bits level > 1 vpp; m=32 bits; 12.5% mark density; <16 consecutive zeroes
idt82v2051e single channel e1 short haul line interface unit functional description 23 december 9, 2005 3.5.2 ais detection the alarm indication signal can be detected by the idt82v2051e when the clock & data recovery unit is enabled. the status of ais detection is reflected in the ais_s bit ( stat0, 17h) . the criteria for declaring/clearing ais detection comply with the itu g.775 or the etsi 300233, as selected by the lac bit ( maint0, 0dh ). table-9 summarizes different criteria for ais detection declaring/clearing. table-8 los declare and clear crit eria, adaptive equalizer enabled control bit los declare thres hold los clear threshold note lac los[4:0] q (db) 0 - 00000 ? 00010 -4 ? -8 level < q n=32 bits level > q+ 4 db m=32 bits 12.5% mark density <16 consecutive zeroes g.775 level detect range is -9 to -35 db. g.775 00011 ? 01010 01011 - 11111 -10 ? -24 reserved 1 - 00000 -4 level < q n=2048 bits level > q+ 4 db m=32 bits 12.5% mark density <16 consecutive zeroes i.431 level detect range is -6 to -20 db. i.431/etsi 00001 ? 01010 01011 - 11111 -6 ? -24 reserved table-9 ais condition itu g.775 (lac bit is set to ?0? by default) etsi 300233 (lac bit is set to ?1?) ais detected less than 3 zeros contained in each of two consecutive 512-bit streams are received less than 3 zeros contained in a 512-bit str eam are received ais cleared 3 or more zeros contained in each of two consecutive 512-bit streams are received 3 or more zeros contained in a 512-bit stream are received
idt82v2051e single channel e1 short haul line interface unit functional description 24 december 9, 2005 3.6 transmit and detect internal patterns the internal patterns (all ones, all zeros and prbs pattern) will be gen- erated and detected by idt82v2051e. tclk is used as the reference clock by default. mclk can also be used as the reference clock by setting the patt_clk bit ( maint0, 0dh ) to ?1?. if the patt_clk bit ( maint0, 0dh ) is set to ?0? and the patt[1:0] bits ( maint0, 0dh ) are set to ?00?, the transmit path will operate in normal mode. when the chip is configured by har dware, the transmit path will operate in normal mode by setting patt[1: 0] pins to ?00?. refer to 5 hardware con- trol pin summary for details. 3.6.1 transmit all ones in transmit direction, the all ones data can be inserted into the data stream when the patt[1:0] bits ( maint0, 0dh ) are set to ?01?. the transmit data stream is output from ttip/tring. in this case, either tclk or mclk can be used as the transmit clock, as selected by the patt_clk bit ( maint0, 0dh ). in hardware control mode, the all ones data can be inserted into the data stream in transmit direction by setting patt[1:0] pins to ?01?. refer to 5 hardware control pin summary for details. 3.6.2 transmit all zeros if the patt_clk bit ( maint0, 0dh ) is set to ?1?, the all zeros will be inserted into the transmit data stream when the patt[1:0] bits ( maint0, 0dh ) are set to ?00?. 3.6.3 prbs generation and detection a prbs will be generated in the transmit direction and detected in the receive direction by idt82v2051e. the prbs is 2 15 -1, with maximum zero restrictions according to itu-t o.151. when the patt[1:0] bits ( maint0, 0dh ) are set to ?10?, the prbs pat- tern will be inserted into the transmit data stream with the msb first. the prbs pattern will be transmitted directly or invertedly. in hardware control mode, the prbs data will be generated in the trans- mit direction and inserted into the tr ansmit data stream by setting patt[1:0] pins to ?10?. refer to 5 hardware control pin summary for details. the prbs in the received data stream will be monitored. if the prbs has reached synchronization status, the prbs_s bit ( stat0, 17h ) will be set to ?1?, even in the presence of a l ogic error rate less than or equal to 10 - 1 . the criteria for setting/cleari ng the prbs_s bit are shown in table-10 . prbs data can be inverted through setting the prbs_inv bit ( maint0, 0dh) . any change of prbs_s bit will be captured by prbs_is bit ( ints0, 19h ). the prbs_ies bit ( intes, 16h ) can be used to determine whether the ?0? to ?1? change of prbs_s bit will be captured by the prbs_is bit or any changes of prbs_s bit will be c aptured by the prbs_is bit. when the prbs_is bit is ?1?, an interrupt will be generated if the prbs_im bit ( intm0, 14h ) is set to ?1?. the received prbs logic errors can be counted in a 16-bit counter if the err_sel [1:0] bits ( maint6, 13h ) are set to ?00?. refer to 3.8 error detec- tion/counting and insertion for the operation of the error counter. 3.7 loopback to facilitate testing and diagnosis, the idt82v2051e provides three dif- ferent loopback configurations: analog loopback, digital loopback and remote loopback. 3.7.1 analog loopback when the alp bit ( maint1, 0eh ) is set to ?1?, the chip is configured in analog loopback mode. in this mode, the transmit signals are looped back to the receiver internal termination in the receive path then output from rclk, rd, rdp/rdn. at the same ti me, the transmit signals are still output to ttip/tring in transmit direction. the all-ones pattern can be generated during analog loopback. figure-11 shows the process. 3.7.2 digital loopback when the dlp bit ( maint1, 0eh ) is set to ?1?, the chip is configured in digital loopback mode. in this mode, the transmit signals are looped back to the jitter attenuator (if enabled) and decoder in receive path, then output from rclk, rd, rdp/rdn. at the same time, the transmit signals are still output to ttip/tring in transmit direction. figure-12 shows the process. both analog loopback mode and digital loopback mode allow the sending of the internal patterns (all o nes, all zeros, prbs, etc.) which will overwrite the transmit signals. in this case, either tclk or mclk can be used as the reference clock for internal patterns transmission. in hardware control mode, digita l loopback can be selected by setting lp[1:0] pins to ?10?. 3.7.3 remote loopback when the rlp bit ( maint1, 0eh ) is set to ?1?, the chip is configured in remote loopback mode. in this mode, the recovered clock and data output from clock and data recovery on the receive path is looped back to the jitter attenuator (if enabled) and waveform shaper in transmit path. figure- 13 shows the process. in hardware control mode, remote loopback can be selected by setting lp[1:0] pins to ?11?. table-10 criteria for setting/clearing the prbs_s bit prbs detection 6 or less than 6 bit errors detected in a 64 bits hopping win- dow. prbs missing more than 6 bit errors detected in a 64 bits hopping window.
idt82v2051e single channel e1 short haul line interface unit functional description 25 december 9, 2005 figure-11 analog loopback figure-12 digital loopback hdb3/ami encoder jitter attenuator line driver waveform shaper hdb3/ami decoder jitter attenuator data slicer adaptive equalizer los/ais detection clock and data recovery transmitter internal termination receiver internal termination tclk tdn td/tdp rclk cv/rdn los rd/rdp rring ttip tring rtip analog loopback hdb3/ami encoder jitter attenuator hdb3/ami decoder jitter attenuator data slicer adaptive equalizer los/ais detection clock and data recovery digital loopback receiver internal termination tclk tdn td/tdp rclk cv/rdn los rd/rdp rring ttip tring rtip line driver waveform shaper transmitter internal termination
idt82v2051e single channel e1 short haul line interface unit functional description 26 december 9, 2005 figure-13 remote loopback hdb3/ami encoder jitter attenuator hdb3/ami decoder jitter attenuator data slicer adaptive equalizer los/ais detection clock and data recovery receiver internal termination tclk tdn td/tdp rclk cv/rdn los rd/rdp rring ttip tring rtip remote loopback line driver waveform shaper transmitter internal termination
idt82v2051e single channel e1 short haul line interface unit functional description 27 december 9, 2005 3.8 error detection/co unting and insertion 3.8.1 definition of line coding error the following line encoding errors can be detected and counted by the idt82v2051e: ? received bipolar violation (bpv) error: in ami coding, when two consecutive pulses of the same pol arity are received, a bpv error is declared. ? hdb3 code violation (cv) error: in hdb3 coding, a cv error is declared when two consecutive bpv errors are detected, and the pulses that have the same polarity as the previous pulse are not the hdb3 zero substitution pulses. ? excess zero (exz) error: ther e are two standards defining the exz errors: ansi and fcc. the exz_def bit ( maint6, 13h ) chooses which standard will be adopt ed by the chip to judge the exz error. table-11 shows definition of exz. in hardware control mode, only ansi standard is adopted. 3.8.2 error detection and counting which type of the receiving errors (received cv/bpv errors, excess zero errors and prbs logic errors ) will be counted is determined by err_sel[1:0] bits ( maint6, 13h ). only one type of receiving error can be counted at a time except that when t he err_sel[1:0] bits are set to ?11?, both cv/bpv and exz errors will be detected and counted. the selected type of receiving errors is counted in an internal 16-bit error counter. once an error is detected, an error interrupt which is indicated by corresponding bit in ( ints1, 1ah ) will be generated if it is not masked. this error counter can be operated in two modes: auto report mode and man- ual report mode, as selected by the cnt_md bit ( maint6, 13h ). in single rail mode, once bpv or cv errors are detected, the cv pin will be driven to high for one rclk period. ? auto report mode in auto report mode, the internal c ounter starts to count the received errors when the cnt_md bit ( maint6, 13h ) is set to ?1?. a one-second timer is used to set the counting period. the received errors are counted within one second. if the one-second timer expires, the value in the internal counter will be transferred to ( cnt0, 1bh ) and ( cnt1, 1ch ), then the inter- nal counter will be reset and start to count received errors for the next sec- ond. the errors occurred during the transfer will be accumulated to the next round. the expiration of the one-second timer will set tmov_is bit ( ints1, 1ah ) to ?1?, and will generate an interrupt if the timer_im bit ( intm1, 15h ) is set to ?0?. the tmov_is bit ( ints1, 1ah ) will be cleared after the interrupt register is read. the content in the ( cnt0, 1bh ) and ( cnt1, 1ch ) should be read within the next second. if the c ounter overflows, a counter overflow interrupt which is indica ted by cnt_ov_is bit ( ints1, 1ah ) will be gener- ated if it is not masked by cnt_im bit ( intm1, 15h ). figure-14 auto report mode table-11 exz definition exz definition ansi fcc ami more than 15 consecutive 0s are detected more than 80 consecutive 0s are detected hdb3 more than 3 consecutive 0s are detected more than 3 consecutive 0s are detected one-second timer expired? counting auto report mode (cnt_md=1) bit tmov_is is set to '1' y n cnt0, cnt1 data in counter counter 0 read the data in cnt0, cnt1 within the next second next second repeats the same process bit tmov_is is cleared after the interrupt register is read
idt82v2051e single channel e1 short haul line interface unit functional description 28 december 9, 2005 ? manual report mode in manual report mode, the internal error counter starts to count the received errors when the cnt_md bit (maint6, 13h) is set to ?0?. when there is a ?0? to ?1? transition on the cnt_trf bit (maint6, 13h) , the data in the counter will be transferred to (cnt0, 1bh) and (cnt1, 1ch) , then the counter will be reset. the errors occurred during the transfer will be accumulated to the next round. if the c ounter overflows, a counter overflow interrupt indicated by cnt_ov_is bit (ints1, 1ah) will be generated if it is not masked by cnt_im bit (intm1, 15h) . figure-15 manual report mode note: it is recommended that users should do the followings within next round of error counting: read the data in cnt0 and cnt1; reset cnt_trf bit for the next ?0? to ?1? transition on this bit. 3.8.3 bipolar violation and prbs error insertion only when three consecutive ?1?s are detected in the transmit data stream, will a ?0? to ?1? transition on the bpv_ins bit ( maint6, 13h ) generate a bipolar violation pulse, and the polarity of the second ?1? in the series will be inverted. a ?0? to ?1? transition on the eer_ins bit ( maint6, 13h ) will generate a logic error during t he prbs transmission. 3.9 line driver failure monitoring the transmit driver failure monito r can be enabled or disabled by setting dfm_off bit ( tcf1, 06h ). if the transmit driver failure monitor is enabled, the transmit driver failure will be captured by df_s bit ( stat0, 17h ). the transition of the df_s bit is reflected by df_is bit ( ints0, 19h ), and, if enabled by df_im bit ( intm0, 14h ), will generate an interrupt. when there is a short circuit on the ttip/tring port, the output current will be limited to 100 ma (typical), and an interrupt will be generated. in hardware control mode, the transmit driver failure monitor is always enabled. a '0' to '1' transition on cnt_trf? counting manual report mode (cnt_md=0) cnt0, cnt1 data in counter counter 0 y n next round repeat the same process read the data in cnt0, cnt1 within next round 1 reset cnt_trf for the next '0' to '1' transition
idt82v2051e single channel e1 short haul line interface unit functional description 29 december 9, 2005 3.10 mclk and tclk 3.10.1 master clock (mclk) mclk is an independent, free-running re ference clock. mclk is 2.048 mhz. this reference clock is used to generate several internal reference signals: ? timing reference for the integrated clock recovery unit. ? timing reference for the int egrated digital jitter attenuator. ? timing reference for microcontroller interface. ? generation of rclk signal during a loss of signal condition if ais is enabled. ? reference clock during transmit all ones, all zeros and prbs pat- tern if it is selected as the reference clock. for atao and ais, mclk is always used as the reference clock. ? reference clock during transmit al l ones (tao) condition or send- ing prbs in hardware control mode. figure-16 shows the chip operation status in different conditions of mclk and tclk. the missing of mclk will set the ttip/tring to high impedance state. 3.10.2 transmit clock (tclk) tclk is used to sample the transmit data on td/tdp and tdn. the active edge of tclk can be selected by the tclk_sel bit ( tcf0, 05h ). during transmit all ones or prbs patte rns, either tclk or mclk can be used as the reference clock. this is selected by the patt_clk bit ( maint0, 0dh ). but for automatic transmit all ones and ais, only mclk is used as the reference clock and the patt_clk bit is ignored. in automatic transmit all ones condition, the atao bit ( maint0, 0dh ) is set to ?1?. in ais condi- tion, the aise bit ( maint0, 0dh ) is set to ?1?. if tclk has been missing for more than 70 mclk cycles, tclk_los bit ( stat0, 17h ) will be set, and the ttip/tring will become high imped- ance if the chip is not used for remote loopback or is not using mclk to trans- mit internal patterns (taos, all zeros and prbs). when tclk is detected again, tclk_los bit ( stat0, 17h ) will be cleared. the reference fre- quency to detect a tclk loss is derived from mclk. figure-16 tclk operation flowchart transmitter high impedance yes mclk=h/l? normal operation clocked tclk status? l/h clocked generate transmit clock loss interrupt if not masked in software control mode; transmitter high impedance
idt82v2051e single channel e1 short haul line interface unit functional description 30 december 9, 2005 3.11 microcontrol ler interfaces the microcontroller interface provi des access to read and write the reg- isters in the device. the chip suppor ts serial microcontroller interface and two kinds of parallel microcontroller interface: motorola multiplexed mode and intel multiplexed mode. different microcontroller interfaces can be selected by setting mode[1:0] pins to different values. refer to mode1 and mode0 in pin description and microcontroller inte rface timing char- acteristics for details. 3.11.1 parallel microcontroller interface the interface is compatible with motorola or intel microcontroller. when mode[1:0] pins are set to ?10?, para llel-multiplexed-motorola interface is selected. when mode[1:0] pins are set to ?11?, parallel-multiplexed-intel interface is selected. 3.11.2 serial microcontroller interface when mode[1:0] pins are set to ?01?, serial interface is selected. in this mode, the registers are programmed th rough a 16-bit word which contains an 8-bit address/command byte (5 address bits a0~a4 and bit r/ w ) and an 8-bit data byte (d0~d7). when bit r/ w is ?1?, data is read out from pin sdo. when bit r/ w is ?0?, data is written into sdi pin. refer to figure-17 . figure-17 serial microcontroller interface function timing 3.12 interrupt handling all kinds of interrupt of the idt82v2051e are indicated by the int pin. when the int_pin[0] bit ( gcf, 02h ) is ?0?, the int pin is open drain active low, with a 10 k ? external pull-up resistor. when the int_pin[1:0] bits ( gcf, 02h ) are ?01?, the int pin is push-pull active low; when the int_pin[1:0] bits are ?10?, the int pin is push-pull active high. an active level on the int pin represents an interrupt of the idt82v2051e. the interrupt event is captured by the corresponding bit in the interrupt status register (ints0, 19h) or (ints1, 1ah) . every kind of interrupt can be enabled/disabled individually by the corresponding bit in the register (intm0, 14h) or (intm1, 15h) . some event is reflected by the correspond- ing bit in the status register (stat0, 17h ) or (stat1, 18h) , and the inter- rupt trigger edge selection regist er can be used to determine how the status register sets the interrupt status register. after the interrupt status register (ints0, 19h) or (ints1, 1ah) is read, the int pin become inactive. there are totally twelve kinds of events that could be the interrupt source: (1).los detected (2).ais detected (3).driver failure detected (4).tclk loss (5).synchronization status of prbs (6).prbs error detected (7).code violation received (8).excessive zeros received (9).ja fifo overflow/underflow (10).one-second timer expired (11).error counter overflow (12).arbitrary waveform generator overflow table-12 is a summary of all kinds of interrupt and the associated status bit, interrupt status bit, interrupt trigger edge selection bit and interrupt mask bit. r/ w a0 a1 a2 a3 a4 - - d1 d2 d3 d4 d5 d6 d7 cs sclk sdi address/command byte input data byte (r/ w =0) d0 d1 d2 d3 d4 d5 d6 d7 remains high impedance sdo output data byte (r/ w =1) d0
idt82v2051e single channel e1 short haul line interface unit functional description 31 december 9, 2005 3.13 5v tolerant i/o pins all digital input pins will tolerate 5.0 10% volts and are compatible with ttl logic. 3.14 reset operation the chip can be reset in two ways: ? software reset: writing to the rst register ( 01h ) will reset the chip in 1 us. ? hardware reset: asserting the rst pin low for a minimum of 100 ns will reset the chip. during hardware reset, the device requires an active clock on mclk. after reset, all drivers output are in high impedance state, all the internal flip-flops are reset, and all the register s are initialized to default values. 3.15 power supply this chip uses a single 3.3 v power supply. table-12 interrupt event interrupt event status bit (stat0, stat1) interrupt status bit (ints0, ints1) interrupt edge selection bit (intes) interrupt mask bit (intm0, intm1) los detected los_s los_is los_ies los_im ais detected ais_s ais_is ais_ies ais_im driver failure detected df_s df_is df_ies df_im tclk loss tclk_los tclk_los_is tclk_ies tclk_im synchronization status of prbs prbs_s prbs_is prbs_ies prbs_im prbs error err_is err_im code violation received cv_is cv_im excessive zeros received exz_is exz_im ja fifo overflow jaov_is jaov_im ja fifo underflow jaud_is jaud_im one-second timer expired tmov_is timer_im error counter overflow cnt_ov_is cnt_im arbitrary waveform generator overflow dac_ov_is dac_ov_im
idt82v2051e single channel e1 short haul line interface unit programming information 32 december 9, 2005 4 programming information 4.1 register list and map the registers banks include contro l registers, status registers and counter registers. 4.2 reserved registers when writing to registers with rese rved bit locations, the default state must be written to the reserved bi ts to ensure proper device operation. table-13 register list and map address (hex) register r/w map b7 b6 b5 b4 b3 b2 b1 b0 control registers 00 id r id7 id6 id5 id4 id3 id2 id1 id0 01 rst w 02 gcf r/w - - - - - - int_pin1 int_pin0 03 term r/w - - t_term2 t_term1 t_t erm0 r_term2 r_term1 r_term0 04 jacf r/w - - ja_limit jacf1 jacf0 jadp1 jadp0 jabw transmit path control registers 05 tcf0 r/w - - - t_off td_inv tclk_sel t_md1 t_md0 06 tcf1 r/w - - dfm_off thz puls3 puls2 puls1 puls0 07 tcf2 r/w - - scal5 scal4 scal3 scal2 scal1 scal0 08 tcf3 r/w done rw ui1 ui0 samp3 samp2 samp1 samp0 09 tcf4 r/w - wdat6 wdat5 wdat4 wdat3 wdat2 wdat1 wdat0 receive path control registers 0a rcf0 r/w - - - r_off rd_inv rclk_sel r_md1 r_md0 0b rcf1 r/w - eq_on - los4 los3 los2 los1 los0 0c rcf2 r/w - - slice1 slice0 - - mg1 mg0 network diagnostics control registers 0d maint0 r/w - patt1 patt0 patt_clk prbs_inv lac aise atao 0e maint1 r/w - - - - - rlp alp dlp 1f-12 maint2- maint5 r/w---- - --- 13 maint6 r/w - bpv_ins err_ins exz_d ef err_sel1 err_sel0 cnt_md cnt_trf interrupt control registers 14 intm0 r/w - - - prbs_im tclk_im df_im ais_im los_im 15 intm1 r/w dac_ov_im jaov_im jaud_im err_im exz_im cv_im timer_im cnt_im 16 intes r/w - - - prbs_ies tclk_ies df_ies ais_ies los_ies line status register 17 stat0 r - - - prbs_s tclk_los df_s ais_s los_s 18 stat1 r - - rlp_s - - - - - interrupt status register 19 ints0 r - - - prbs_is tclk_l os_is df_is ais_is los_is 1a ints1 r dac_ov_is jaov_is jaud_is e rr_is exz_is cv_is tmov_is cnt_ov_is counter registers 1b cnt0 r bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1c cnt1 r bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
idt82v2051e single channel e1 short haul line interface unit programming information 33 december 9, 2005 4.3 register description 4.3.1 control registers table-14 id: device revision register (r, address = 00h) symbol bit default description id[7:0] 7-0 00h current silicon chip id. table-15 rst: reset register (w, address = 01h) symbol bit default description rst[7:0] 7-0 00h software reset. a write operation on this register will reset all internal registers to their default values, and the status of all ports are set to the default status. the content in this register can not be changed. after reset, all drivers output are in high impedance state. table-16 gcf: global configuration register (r/w, address = 02h) symbol bit default description - 7-2 000000 reserved. int_pin[1:0] 1-0 00 interrupt pin control = x0: open drain, active low (with an external pull-up resistor) = 01: push-pull, active low = 11: push-pull, active high table-17 term: transmit and receive termination configuration register (r/w, address = 03h) symbol bit default description - 7-6 00 reserved. t_term[2:0] 5-3 000 these bits select the internal termination for transmit line impedance matching. = 000: internal 75 ? impedance matching = 001: internal 120 ? impedance matching = 1xx: selects external impedance matching resistors (see table-4 ). r_term[2:0] 2-0 000 these bits select the internal termination for receive line impedance matching. = 000: internal 75 ? impedance matching = 001: internal 120 ? impedance matching = 1xx: selects external impedance matching resistors (see table-5 ).
idt82v2051e single channel e1 short haul line interface unit programming information 34 december 9, 2005 table-18 jacf: jitter attenuation configuration register (r/w, address = 04h) symbol bit default description - 7-6 00 reserved. ja_limit 5 1 = 0: normal mode = 1: ja limit mode jacf[1:0] 4-3 00 jitter attenuation configuration = 00/10: ja not used = 01: ja in transmit path = 11: ja in receive path jadp[1:0] 2-1 00 jitter attenuation depth select = 00: 128 bits = 01: 64 bits = 1x: 32 bits jabw 0 0 jitter transfer function bandwidth select = 0: 6.8 hz = 1: 0.9 hz
idt82v2051e single channel e1 short haul line interface unit programming information 35 december 9, 2005 4.3.2 transmit path control registers 1. in internal impedance matching mode, for e1/75 ? cable impedance, the puls[3:0] bits ( tcf1, 06h ) should be set to ?0000?. in external impedance matching mode, for e1/75 ? cable impedance, the puls[3:0] bits should be set to ?0001?. table-19 tcf0: transmitter configuration register 0 (r/w, address = 05h) symbol bit default description - 7-5 000 reserved. t_off 4 0 transmitter power down enable = 0: transmitter power up = 1: transmitter power down (line driver high impedance) td_inv 3 0 transmit data invert = 0: data on td or tdp/tdn is active high = 1: data on td or tdp/tdn is active low tclk_sel 2 0 transmit clock edge select = 0: data on tdp/tdn is sampled on the falling edge of tclk = 1: data on tdp/tdn is sampled on the rising edge of tclk t_md[1:0] 0-1 00 transmitter operation mode control t_md[1:0] select different stages of the transmit data path = 00: enable hdb3 encoder and waveform shaper blocks. input on pin td is single rail nrz data = 01: enable ami encoder and waveform shaper blocks. input on pin td is single rail nrz data = 1x: encoder is bypassed, dual rail nrz transmit data input on pin tdp/tdn table-20 tcf1: transmitter configuration register 1 (r/w, address = 06h) symbol bit default description - 7-6 00 reserved. this bit should be ?0? for normal operation. dfm_off 5 0 transmit driver failure monitor disable = 0: dfm is enabled = 1: dfm is disabled thz 4 1 transmit line driver high impedance enable = 0: normal state = 1: transmit line driver high impedance enable (other transmit path still work normally) puls[3:0] 3-0 0000 these bits select the transmit template: tclk cable impedance allowable cable loss 0000 1 2.048 mhz 75 ? 0-24 db 0001 2.048 mhz 120 ? 0-24 db 0010 - 1011 reserved 11xx user programmable waveform setting table-21 tcf2: transmitter configuration register 2 (r/w, address = 07h) symbol bit default description - 7-6 00 reserved. scal[5:0] 5-0 100001 scal specifies a scaling factor to be applied to the amplitude of the user-programmable arbitrary pulses whic h is to be transmitted if needed. the default value of scal[5:0] is ?100001?. refer to 3.2.3.2 user-programmable arbi- trary waveform . = 100001: default value for 75 ? and 120 ? . one step change of this value results in 3% scaling up/down against the pulse amplitude.
idt82v2051e single channel e1 short haul line interface unit programming information 36 december 9, 2005 table-22 tcf3: transmitter configuration register 3 (r/w, address = 08h) symbol bit default description done 7 0 after ?1? is written to this bit, a read or write operation is implemented. rw 6 0 this bit selects read or write operation = 0: write to ram = 1: read from ram ui[1:0] 5-4 00 these bits specify the unit interval address. there are totally 4 unit intervals. = 00: ui address is 0 (the most left ui) = 01: ui address is 1 = 10: ui address is 2 = 11: ui address is 3 samp[3:0] 3-0 0000 these bits specify the sample address. each ui has totally 16 samples. = 0000: sample address is 0 (the most left sample) = 0001: sample address is 1 = 0010: sample address is 2 ?? = 1110: sample address is 14 = 1111: sample address is 15 table-23 tcf4: transmitter configuration register 4 (r/w, address = 09h) symbol bit default description -70reserved wdat[6:0] 6-0 0000000 in indirect write operation, the wdat[6:0] will be loaded to the pulse template ram, specifying the amplitud e of the sample. after an indirect read operation, the amplitude data of the sample in the pulse template ram will be output to the wdat[6:0].
idt82v2051e single channel e1 short haul line interface unit programming information 37 december 9, 2005 4.3.3 receive path control registers table-24 rcf0: receiver configuration register 0 (r/w, address = 0ah) symbol bit default description - 7-5 000 reserved r_off 4 0 receiver power down enable = 0: receiver power up = 1: receiver power down rd_inv 3 0 receive data invert = 0: data on rd or rdp/rdn is active high = 1: data on rd or rdp/rdn is active low rclk_sel 2 0 receive clock edge select (this bit is ignored in slicer mode) = 0: data on rd or rdp/rdn is updated on the rising edge of rclk = 1: data on rd or rdp/rdn is updated on the falling edge of rclk r_md[1:0] 1-0 00 receive path decoding selection = 00: receive data is hdb3 decoded and output on rd pin with single rail nrz format = 01: receive data is ami decoded and output on rd pin with single rail nrz format = 10: decoder is bypassed, re-timed dual rail data with nrz format output on rdp/rdn (dual rail mode with clock recovery) = 11: cdr and decoder are bypassed, slicer data with rz format output on rdp/rdn (slicer mode) table-25 rcf1: receiver configuration register 1 (r/w, address= 0bh) symbol bit default description -70reserved eq_on 6 0 = 0: receive equalizer off = 1: receive equalizer on (los programming enabled) - 5 0 reserved. los[4:0] 4:0 10101 los clear level (db) los declare level (db) 00000 0 <-4 00001 >-2 <-6 00010 >-4 <-8 00011 >-6 <-10 00100 >-8 <-12 00101 >-10 <-14 00110 >-12 <-16 00111 >-14 <-18 01000 >-16 <-20 01001 >-18 <-22 01010 >-20 <-24 01011 - 11111 reserved
idt82v2051e single channel e1 short haul line interface unit programming information 38 december 9, 2005 table-26 rcf2: receiver configuration register 2 (r/w, address = 0ch) symbol bit default description - 7-6 00 reserved. slice[1:0] 5-4 01 receive slicer threshold = 00: the receive slicer generates a mark if the voltage on rtip/rring exceeds 40% of the peak amplitude. = 01: the receive slicer generates a mark if the voltage on rtip/rring exceeds 50% of the peak amplitude. = 10: the receive slicer generates a mark if the voltage on rtip/rring exceeds 60% of the peak amplitude. = 11: the receive slicer generates a mark if the voltage on rtip/rring exceeds 70% of the peak amplitude. - 3-2 10 reserved mg[1:0] 1-0 00 monitor gain setting: these bits select the internal linear gain boost = 00: 0 db = 01: 22 db = 10: 26 db = 11: 32 db
idt82v2051e single channel e1 short haul line interface unit programming information 39 december 9, 2005 4.3.4 network diagnost ics control registers table-27 maint0: maintenance function control register 0 (r/w, address = 0dh) symbol bit default description - 7 00 reserved. patt[1:0] 6-5 00 these bits select the internal pattern and insert it into transmit data stream. = 00: normal operation (patt_clk = 0) / insert all zeros (patt_clk = 1) = 01: insert all ones = 10: insert prbs (e1: 2 15 -1) = 11: reserved patt_clk 4 0 selects reference clock for transmitting internal pattern = 0: uses tclk as the reference clock = 1: uses mclk as the reference clock prbs_inv 3 0 inverts prbs = 0: the prbs data is not inverted = 1: the prbs data is inverted before transmission and detection lac 2 0 los/ais criterion is selected as below: = 0: g.775 = 1: etsi 300233& i.431 aise 1 0 ais enable during los = 0: ais insertion on rdp/rdn/rclk is disabled during los = 1: ais insertion on rdp/rdn/rclk is enabled during los atao 0 0 automatically transmit all ones (enabled only when patt[1:0] = 00) = 0: disabled = 1: automatically transmit all ones pattern at ttip/tring during los table-28 maint1: maintenance function control register 1 (r/w, address= 0eh) symbol bit default description - 7-3 00000 reserved rlp 2 0 remote loopback enable = 0: disables remote loopback (normal transmit and receive operation) = 1: enables remote loopback alp 1 0 analog loopback enable = 0: disables analog loopback (normal transmit and receive operation) = 1: enables analog loopback dlp 0 0 digital loopback enable = 0: disables digital loopback (normal transmit and receive operation) = 1: enables digital loopback table-29 maint6: maintenance function control register 6 (r/w, address = 13h) symbol bit default description - 7 0 reserved. bpv_ins 6 0 bpv error insertion a ?0? to ?1? transition on this bit will cause a single bipolar violation error to be inserted into the transmit data stream. this bit must be cleared and set again for a subsequent error to be inserted. err_ins 5 0 prbs logic error insertion a ?0? to ?1? transition on this bit will cause a single prbs logic error to be inserted into the transmit prbs data stream. this bit must be cleared and set again for a subsequent error to be inserted.
idt82v2051e single channel e1 short haul line interface unit programming information 40 december 9, 2005 exz_def 5 0 exz definition select = 0: ansi = 1: fcc err_sel 3-2 00 these bits choose which type of error will be counted = 00: the prbs logic error is counted by a 16-bit error counter. = 01: the exz error is counted by a 16-bit error counter. = 10: the received cv (bpv) error is counted by a 16-bit error counter. = 11: both cv (bpv) and exz errors are counted by a 16- bit error counter. cnt_md 1 0 counter operation mode select = 0: manual report mode = 1: auto report mode cnt_trf 0 0 = 0: clear this bit for the next ?0? to ?1? transition on this bit. = 1: error counting result is transferred to cnt0 and cnt1 and the error counter is reset. table-29 maint6: maintenance function control register 6 (continued) (r/w, address = 13h) symbol bit default description
idt82v2051e single channel e1 short haul line interface unit programming information 41 december 9, 2005 4.3.5 interrupt control registers table-30 intm0: interrupt mask register 0 (r/w, address = 14h) symbol bit default description -7-5111reserved prbs_im 4 1 prbs synchronic signal detect interrupt mask = 0: prbs synchronic signal detect interrupt enabled = 1: prbs synchronic signal detect interrupt masked tclk_im 3 1 tclk loss detect interrupt mask = 0: tclk loss detect interrupt enabled = 1: tclk loss detect interrupt masked df_im 2 1 driver fail ure interrupt mask = 0: driver failure interrupt enabled = 1: driver failure interrupt masked ais_im 1 1 alarm indication signal interrupt mask = 0: alarm indication signal interrupt enabled = 1: alarm indication signal interrupt masked los_im 0 1 loss of signal interrupt mask = 0: loss of signal interrupt enabled = 1: loss of signal interrupt masked table-31 intm1: interrupt masked register 1 (r/w, address = 15h) symbol bit default description dac_ov_im 7 1 dac arithmetic overflow interrupt mask = 0: dac arithmetic overflow interrupt enabled = 1: dac arithmetic overflow interrupt masked jaov_im 6 1 ja overflow interrupt mask = 0: ja overflow interrupt enabled = 1: ja overflow interrupt masked jaud_im 5 1 ja underflow interrupt mask = 0: ja underflow interrupt enabled = 1: ja underflow interrupt masked err_im 4 1 prbs logic error detect interrupt mask = 0: prbs logic error detect interrupt enabled = 1: prbs logic error de tect interrupt masked exz_im 3 1 receive excess zeros interrupt mask = 0: receive excess zeros interrupt enabled = 1: receive excess zeros interrupt masked cv_im 2 1 receive error interrupt mask = 0: receive error interrupt enabled = 1: receive error interrupt masked timer_im 1 1 one-second timer expiration interrupt mask = 0: one-second timer expiration interrupt enabled = 1: one-second timer expiration interrupt masked cnt_im 0 1 counter overflow interrupt mask = 0: counter overflow interrupt enabled = 1: counter overflow interrupt masked
idt82v2051e single channel e1 short haul line interface unit programming information 42 december 9, 2005 table-32 intes: interrupt trigger edge select register (r/w, address = 16h) symbol bit default description - 7-5 000 reserved prbs_ies 4 0 this bit determines the prbs synchronization status interrupt event. = 0: interrupt event is generated as a ?0? to ?1? transition of the prbs_s bit in stat0 status register = 1: interrupt event is generated as either a ?0? to ?1? transition or a ?1? to ?0? transition of the prbs_s bit in stat0 status register tclk_ies 3 0 this bit determines the tclk loss interrupt event. = 0: interrupt event is generated as a ?0? to ?1? transition of the tclk_los bit in stat0 status register = 1: interrupt event is generated as either a ?0? to ?1? transition or a ?1? to ?0? transition of the tclk_los bit in stat0 status register df_ies 2 0 this bit determines the driver failure interrupt event. = 0: interrupt event is generated as a ?0? to ?1? transition of the df_s bit in stat0 status register = 1: interrupt event is generated as either a ?0? to ?1? transition or a ?1? to ?0? transition of the df_s bit in stat0 status register ais_ies 1 0 this bit determines the ais interrupt event. = 0: interrupt event is generated as a ?0? to ?1? transition of the ais_s bit in stat0 status register = 1: interrupt event is generated as either a ?0? to ?1? transition or a ?1? to ?0? transition of the ais_s bit in stat0 status register los_ies 0 0 this bit determines the los interrupt event. = 0: interrupt is generated as a ?0? to ?1? transition of the los_s bit in stat0 status register = 1: interrupt is generated as either a ?0? to ?1? transition or a ?1? to ?0? transition of the los_s bit in stat0 status register
idt82v2051e single channel e1 short haul line interface unit programming information 43 december 9, 2005 4.3.6 line status registers table-33 stat0: line status register 0 (real time status monitor) (r, address = 17h) symbol bit default description - 7-5 000 reserved prbs_s 4 0 synchronous status indi cation of prbs (real time) = 0: 2 15 -1 prbs is not detected = 1: 2 15 -1 prbs is detected note: if prbs_im=0: a ?0? to ?1? transition on this bit causes a synchronous status detected interrupt if prbs _ies bit is ?0?. any changes of this bit causes an interrupt if prbs_ies bit is set to ?1?. tclk_los 3 0 tclk loss indication = 0: normal = 1: tclk pin has not toggled for more than 70 mclk cycles. note: if tclk_im=0: a ?0? to ?1? transition on this bit causes an interrupt if tclk _ies bit is ?0?. any changes of this bit causes an interrupt if tclk_ies bit is set to ?1?. df_s 2 0 line driver status indication = 0: normal operation = 1: line driver short circuit is detected. note: if df_im=0 a ?0? to ?1? transition on this bit causes an interrupt if df _ies bit is ?0?. any changes of this bit causes an interrupt if df_ies bit is set to ?1?. ais_s 1 0 alarm indication signal status detection = 0: no ais signal is detected in the receive path = 1: ais signal is detected in the receive path note: if ais_im=0 a ?0? to ?1? transition on this bit causes an interrupt if ais _ies bit is ?0?. any changes of this bit causes an interrupt if ais_ies bit is set to ?1?. los_s 0 0 loss of signal status detection = 0: loss of signal on rtip/rring is not detected. = 1: loss of signal on rtip/rring is detected. note: if los_im=0 a ?0? to ?1? transition on this bit causes an interrupt if los _ies bit is ?0?. any changes of this bit causes an interrupt if los_ies bit is set to ?1?.
idt82v2051e single channel e1 short haul line interface unit programming information 44 december 9, 2005 table-34 stat1: line status register 1 (real time status monitor) (r, address = 18h) symbol bit default description - 7-6 00 reserved. rlp_s 5 0 indicating the status of remote loopback = 0: the remote loopback is inactive. = 1: the remote loopback is active (closed). - 4-0 00000 reserved
idt82v2051e single channel e1 short haul line interface unit programming information 45 december 9, 2005 4.3.7 interrupt status registers table-35 ints0: interrupt status register 0 (r, address = 19h) (thi s register is reset and relevant inte rrupt request is cleared after a read) symbol bit default description - 7-5 000 reserved prbs_is 4 0 this bit indicates the occurrence of the interrupt event generated by the prbs synchronization status. = 0: no prbs synchronization status interrupt event occurred = 1: prbs synchronization status interrupt event occurred tclk_los_is 3 0 this bit indicates the occurrence of the interrupt event generated by the tclk loss detection. = 0: no tclk loss interrupt event. = 1: tclk loss interrupt event occurred. df_is 2 0 this bit indicates the occurrence of the interrupt event generated by the driver failure. = 0: no driver failure interrupt event occurred = 1: driver failure interrupt event occurred ais_is 1 0 this bit indicates the occurrence of the ais (alarm indication signal) interrupt event. = 0: no ais interrupt event occurred = 1: ais interrupt event occurred los_is 0 0 this bit indicates the occurrence of the los (loss of signal) interrupt event. = 0: no los interrupt event occurred = 1: los interrupt event occurred table-36 ints1: interrupt status register 1 (r, address = 1ah) (this register is rese t and the relevant interrupt request is cleared after a read) symbol bit default description dac_ov_is 7 0 this bit indicates the occurrence of the pulse amplit ude overflow of arbitrary waveform generator interrupt event. = 0: no pulse amplitude overflow of arbitrar y waveform generator interrupt event occurred = 1: the pulse amplitude overflow of arbitrary waveform generator interrupt event occurred jaov_is 6 0 this bit indicates the occurrence of the jitter attenuator overflow interrupt event. = 0: no ja overflow interrupt event occurred = 1: ja overflow interrupt event occurred jaud_is 5 0 this bit indicates the occurrence of the jitter attenuator underflow interrupt event. = 0: no ja underflow interrupt event occurred = 1: ja underflow interrupt event occurred err_is 4 0 this bit indicates the occurrence of the interrupt event generated by the detected prbs logic error. = 0: no prbs logic error interrupt event occurred = 1: prbs logic error interrupt event occurred exz_is 3 0 this bit indicates the occurrence of the excessive zeros interrupt event. = 0: no excessive zeros interrupt event occurred = 1: exz interrupt event occurred cv_is 2 0 this bit indicates the occurrence of the code violation interrupt event. = 0: no code violation interrupt event occurred = 1: code violation interrupt event occurred tmov_is 1 0 this bit indicates the occurrence of the one-second timer expiration interrupt event. = 0: no one-second timer expiration interrupt event occurred = 1: one-second timer expiration interrupt event occurred cnt_ov_is 0 0 this bit indicates the occurrence of the counter overflow interrupt event. = 0: no counter overflow interrupt event occurred = 1: counter overflow interrupt event occurred
idt82v2051e single channel e1 short haul line interface unit programming information 46 december 9, 2005 4.3.8 counter registers table-37 cnt0: error counter l-byte register 0 (r, address = 1bh) symbol bit default description cnt_l[7:0] 7-0 00h this register contains the lower eight bits of the 16-bit error counter. cnt_l[0] is the lsb. table-38 cnt1: error counter h-byte register 1 (r, address = 1ch) symbol bit default description cnt_h[7:0] 7-0 00h this register contains the upper eight bits of the 16-bit error counter. cnt_h[7] is the msb.
idt82v2051e single channel e1 short haul line interface unit hardware control pin summary 47 december 9, 2005 5 hardware control pin summary table-39 hardware control pin summary pin no. tqfp symbol description 17 16 mode1 mode0 mode[1:0]: operation mode of control interface select 00= hardware interface 01= serial interface 10= parallel ? multiplexed ? motorola interface 11= parallel ? multiplexed ? intel interface 23 term term: termination interface select this pin selects internal or external impedance matching for both receiver and transmitter 0= ternary interface with external impedance matching network. 1= ternary interface with internal impedance matching network 21 20 rxtxm1 rxtxm0 rxtxm[1:0]: receive and transm it path operation mode select 00= single rail with hdb3 coding 01= single rail with ami coding 10= dual rail interface with cdr enable 11= slicer mode 30 puls puls: this pin is used to select the following functions: ? transmit pulse template ? internal termination impedance (75 ? / 120 ? ) puls tclk cable impedance (interna l matching impedance) cable loss 0 2.048 mhz 75 ? 0-24 db 1 2.048 mhz 120 ? 0-24 db 28 rpd rpd: receiver power down control 0= normal operation 1= receiver power down 27 26 patt1 patt0 patt[1:0]: transmit test pattern select in hardware control mode, these pins select the transmit pattern 00 = normal 01= all ones 10= prbs 11= transmitter power down 15 14 ja1 ja0 ja[1:0]: jitter attenuation position, band width and the depth of fifo select 00= ja is disabled 01= ja in receiver, broad bandwidth, fifo=64 bits 10= ja in receiver, narrow bandwidth, fifo=128 bits 11= ja in transmitter, narrow bandwidth, fifo=128 bits 22 mont mont: receive monitor n gain select 0= 0 db 1= up to 26 db 25 24 lp1 lp0 lp[1:0]: loopback mode select 00= no loopback 01= analog loopback 10= digital loopback 11= remote loopback 13 thz thz: transmitter driver high impedance enable this signal enables or disables transmitter driver. a low level on this pin enables the driver while a high level on this pin p laces the driver in high impedance state. 11 rclke rclke: the active edge of rclk select when hardware control mode is used 0= select the rising edge as active edge of rclk 1= select the falling edge as active edge of rclk
idt82v2051e single channel e1 short haul line interface unit hardware control pin summary 48 december 9, 2005 29 31 32 33 - in hardware mode, this pin has to be tied to gnd. table-39 hardware control pin summary (continued) pin no. tqfp symbol description
idt82v2051e single channel e1 short haul line interface unit test specifications 49 december 9, 2005 6 test specifications 1.reference to ground 2.human body model 3.charge device model 4.constant input current 1.power consumption includes power consumption on device and lo ad. digital levels are 10% of the supply rails and digital outpu ts driving a 50 pf capacitive load. 2.maximum power consumption over the full operat ing temperature and power supply voltage range. 3.in short haul mode, if internal impedance matching is chosen, 75 ? power dissipation values are measur ed with template puls[3:0] = 0000; 120 ? power dissipation values are measured with template puls[3:0] = 0001. table-40 absolute maximum rating symbol parameter min max unit vdda, vddd core power supply -0.5 4.6 v vddio i/o power supply -0.5 4.6 v vddt transmit power supply -0.5 4.6 v vin input voltage, any digital pin gnd-0.5 5.5 v input voltage, any rtip and rring pin 1 gnd-0.5 vdda+0.5 v esd voltage, any pin 2000 2 v 500 3 v iin transient latch-up current, any pin 100 ma input current, any digital pin 4 -10 10 ma dc input current, any analog pin 4 100 ma pd maximum power dissipation in package 1.41 w tc case temperature 120 c ts storage temperature -65 +150 c caution: exceeding these values may cause permanent damage. functional operation under these conditions is not implied. exposure to abso lute maximum rating conditions for extended periods may affect device reliability. table-41 recommended operation conditions symbol parameter min typ max unit vdda, vddd core power supply 3.13 3.3 3.47 v vddio i/o power supply 3.13 3.3 3.47 v vddt transmitter power supply 3.13 3.3 3.47 v ta ambient operating temperature -40 25 85 c total current dissipation 1,2,3 75 ? load 50% ones density data 100% ones density data - - 52 64 58 70 ma 120 ? load 50% ones density data 100% ones density data - - 58 70 64 76 ma
idt82v2051e single channel e1 short haul line interface unit test specifications 50 december 9, 2005 1.maximum power and current consumption over the full operating temperature and power supply voltage range. 2.power consumption includes power absorbed by line load and external transmitter components. table-42 power consumption symbol parameter min typ max 1,2 unit 3.3 v, 75 ? load 50% ones density data: 100% ones density data: - - 172 212 - 243 mw 3.3 v, 120 ? load 50% ones density data: 100% ones density data: - - 192 243 - 264 mw table-43 dc characteristics symbol parameter min typ max unit v il input low level voltage - - 0.8 v v ih input high voltage 2.0 - - v v ol output low level voltage (iout=1.6ma) - - 0.4 v v oh output high level voltage (iout=400 a) 2.4 - vddio v v ma analog input quiescent voltage (rtip, rring pin while floating) 1.5 v i zl high impedance leakage current -10 10 a ci input capacitance 15 pf co output load capacitance 50 pf co output load capacitance (bus pins) 100 pf table-44 receiver electrical characteristics symbol parameter min typ max unit test conditions receiver sensitivity adaptive equalizer disabled: adaptive equalizer enabled: -10 -20 db analog los level adaptive equalizer disabled: adaptive equalizer enabled: -4 800 -24 mvp-p db a los level is programmable with adaptive equalizer enabled. not available in hardware mode.
idt82v2051e single channel e1 short haul line interface unit test specifications 51 december 9, 2005 allowable consecutive zeros before los g.775: i.431/etsi300233: 32 2048 los reset 12.5 % ones g.775, etsi 300 233 receive intrinsic jitter 20 hz - 100 khz 0.05 u.i. ja enabled input jitter tolerance 1 hz ? 20 hz 20 hz ? 2.4 khz 18 khz ? 100 khz 37 5 2 u.i. u.i. u.i. g.823, with 6 db cable attenuation zdm receiver differential input impedance 20 k ? internal mode input termination resistor tolerance 1% rrx receive return loss 51 khz ? 102 khz 102 khz ? 2.048 mhz 2.048 mhz ? 3.072 mhz 20 20 20 db db db g.703 internal termination rpd receive path delay single rail dual rail 7 2 u.i. u.i. ja disabled table-45 transmitter electrical characteristics symbol parameter min typ max unit vo-p output pulse amplitudes 75 ? load 120 ? load 2.14 2.7 2.37 3.0 2.60 3.3 v v vo-s zero (space) level 75 ? load 120 ? load -0.237 -0.3 0.237 0.3 v v transmit amplitude variation with supply -1 +1 % difference between pulse sequences for 17 consecutive pulses (t1.102) 200 mv tpw output pulse width at 50% of nominal amplitude 232 244 256 ns ratio of the amplitudes of positive and negative pulses at the center of the pulse interval (g.703) 0.95 1.05 ratio of the width of positive and negative pulses at the center of the pulse interval (g.703) 0.95 1.05 rtx transmit return loss (g.703) 51 khz ? 102 khz 102 khz - 2.048 mhz 2.048 mhz ? 3.072 mhz 20 15 12 db db db jtxp-p intrinsic transmit jitter (tclk is jitter free) 20 hz ? 100 khz 0.050 u.i. td transmit path delay (ja is disabled) single rail dual rail 8.5 4.5 u.i. u.i. isc line short circuit current (measured on the ttip/tring pins) 100 map table-44 receiver electrical characteristics (continued) symbol parameter min typ max unit test conditions
idt82v2051e single channel e1 short haul line interface unit test specifications 52 december 9, 2005 1.relative to nominal frequency, mclk= 100 ppm 2.rclk duty cycle widths will vary depending on extent of received pulse jitter displacement. maximum and minimum rclk duty cyc les are for worst case jitter conditions (0.2 ui displacement for e1 per itu g.823). 3.for all digital outputs. c load = 15 pf figure-18 transmit system interface timing table-46 transmitter and receiver timing characteristics symbol parameter min typ max unit mclk frequency 2.048 mhz mclk tolerance -100 100 ppm mclk duty cycle 30 70 % transmit path tclk frequency 2.048 mhz tclk tolerance -50 +50 ppm tclk duty cycle 10 90 % t1 transmit data setup time 40 ns t2 transmit data hold time 40 ns delay time of thz low to driver high impedance 10 us delay time of tclk low to driver high impedance 75 u.i. receive path clock recovery capture range 1 80 ppm rclk duty cycle 2 40 50 60 % t4 rclk pulse width 2 457 488 519 ns t5 rclk pulse width low time 203 244 285 ns t6 rclk pulse width high time 203 244 285 ns rise/fall time 3 20 ns t7 receive data setup time 200 244 ns t8 receive data hold time 200 244 ns tdn td/tdp tclk t1 t2
idt82v2051e single channel e1 short haul line interface unit test specifications 53 december 9, 2005 figure-19 receive system interface timing table-47 jitter tolerance jitter tolerance min typ max unit standard 1 hz 20 hz ? 2.4 khz 18 khz ? 100 khz 37 1.5 0.2 u.i. u.i. u.i. g.823 cable attenuation is 6 db rdn/cv rdp/rd rclk t4 t7 t6 t7 t5 t8 t8 rdp/rd rdn/cv (rclk_sel = 0 software mode) (rclke = 0 hardware mode) (rclk_sel = 1 software mode) (rclke = 1 hardware mode)
idt82v2051e single channel e1 short haul line interface unit test specifications 54 december 9, 2005 figure-20 e1 jitter tolerance performance table-48 jitter attenuator characteristics parameter min typ max unit jitter transfer function corner (-3 db) frequency 32/64/128 bits fifo jabw = 0: jabw = 1: 6.8 0.9 hz hz jitter attenuator (g.736) @ 3 hz @ 40 hz @ 400 hz @ 100 khz -0.5 -0.5 +19.5 +19.5 db jitter attenuator latency delay 32 bits fifo: 64 bits fifo: 128 bits fifo: 16 32 64 u.i. u.i. u.i. input jitter tolerance before fifo overflow or underflow 32 bits fifo: 64 bits fifo: 128 bits fifo: 28 58 120 u.i. u.i. u.i.
idt82v2051e single channel e1 short haul line interface unit test specifications 55 december 9, 2005 figure-21 e1 jitter transfer performance
idt82v2051e single channel e1 short haul line interface unit microcontroller interface timing characteristics 56 december 9, 2005 7 microcontroller interfac e timing characteristics 7.1 serial interface timing figure-22 serial interface write timing figure-23 serial interface read timing with sclke=1 figure-24 serial interface read timing with sclke=0 table-49 serial interface timing characteristics symbol parameter min typ max unit comments t1 sclk high time 100 ns t2 sclk low time 100 ns t3 active cs to sclk setup time 5 ns t4 last sclk hold time to inactive cs time 41 ns t5 cs idle time 41 ns t6 sdi to sclk setup time 0 ns t7 sclk to sdi hold time 82 ns t10 sclk to sdo valid delay time 95 ns t11 inactive cs to sdo high impedance hold time 90 ns msb lsb lsb cs sclk sdi t1 t2 t3 t4 t5 t6 t7 t7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sdo cs sclk t11 t4 7 6 5 4 3 2 1 0 t10 1 2 3 4 5 6 7 8 9 10111213141516 sdo cs sclk t4 t11 7 6 5 4 3 2 1 0 t10
idt82v2051e single channel e1 short haul line interface unit microcontroller interface timing characteristics 57 december 9, 2005 7.2 parallel interface timing figure-25 mu ltiplexed motorola read timing table-50 multiplexed motorola read timing characteristics symbol parameter min max unit trc read cycle time 190 ns tdw valid ds width 180 ns trwv delay from ds to valid read 15 ns trwh r/ w to ds hold time 65 ns tasw valid as width 10 ns tadd delay from as active to ds active 0 ns tads address to as setup time 5 ns tadh address to as hold time 5 ns tprd ds to valid read data propagation delay 175 ns tdaz delay from ds inactive to data bus high impedance 5 20 ns takd acknowledgement delay 190 ns takh acknowledgement hold time 5 15 ns takz acknowledgement release time 5 ns trecovery recovery time from read cycle 5 ns ds + cs r/ w read ad[7:0] trwv valid data tdaz trwh tprd tdw tasw tadd tads tadh valid address as takd takh ack takz trc trecovery
idt82v2051e single channel e1 short haul line interface unit microcontroller interface timing characteristics 58 december 9, 2005 figure-26 multiplexed motorola write timing table-51 multiplexed motorola write timing characteristics symbol parameter min max unit twc write cycle time 120 ns tdw valid ds width 100 ns trwv delay from ds to valid write 15 ns trwh r/ w to ds hold time 65 ns tasw valid as width 10 ns tadd delay from as active to ds active 0 ns tads address to as setup time 5 ns tadh address to as hold time 5 ns tdv delay from ds to valid write data 15 ns tdhw write data to ds hold time 65 ns takd acknowledgement delay 150 ns takh acknowledgement hold time 5 15 ns takz acknowledgement release time 5 ns trecovery recovery time from write cycle 5 ds + cs r/ w write ad[7:0] trwv valid data tdhw trwh tdv tdw tasw tadd tads tadh valid address as takd takh ack takz twc trecovery
idt82v2051e single channel e1 short haul line interface unit microcontroller interface timing characteristics 59 december 9, 2005 figure-27 multiplexed intel read timing table-52 multiplexed intel read timing characteristics symbol parameter min max unit trc read cycle time 190 ns trdw valid rd width 180 ns tard delay from ale to valid read 0 ns talew valid ale width 10 ns tads address to ale setup time 5 ns tadh address to ale hold time 5 ns tprd rd to valid read data propagation delay 175 ns tdaz delay from rd inactive to data bus high impedance 5 20 ns takd acknowledgement delay 190 ns takh acknowledgement hold time 5 15 ns takz acknowledgement release time 5 ns trecovery recovery time fr om read cycle 5 rd + cs read ad[7:0] valid data tdaz tprd trdw talew tard tads tadh valid address ale takd takh rdy takz trc trecovery
idt82v2051e single channel e1 short haul line interface unit microcontroller interface timing characteristics 60 december 9, 2005 figure-28 multiple xed intel write timing table-53 multiplexed intel write timing characteristics symbol parameter min max unit twc write cycle time 120 ns twrw valid wr width 100 ns talew valid ale width 10 ns tawd delay from ale to valid write 0 ns tads address to ale setup time 5 ns tadh address to ale hold time 5 ns tdv delay from wr to valid write data 15 ns tdhw write data to wr hold time 65 ns takd acknowledgement delay 150 ns takh acknowledgement hold time 5 15 ns takz acknowledgement release time 5 ns trecovery recovery time from write cycle 5 wr + cs write ad[7:0] valid data tdhw tdv twrw talew tawd tads tadh valid address ale takd takh rdy takz twc trecovery
idt82p2816 high-density t1/e 1/j1 line interface unit idt82v2051e single channel e1 short haul line interface unit 61 corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: 408-360-1552 email:telecomhelp@idt.com ordering information datasheet document history 12/09/2005 pgs. 1, 14, 18, 24, 31, 32, 39, 51, 52, 61 idt xxxxxxx xx x device type blank process/ temperature range pp 82v2051e industrial (-40 c to +85 c) thin quad flatpack (tqfp, pp44) short haul liu green thin quad flatpack (tqfp, ppg44) ppg

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